MFC2000 datasheet(301/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

16-3

Bit 13:

This bit indicates that the FIFO can accept data transfers to/from the

local logic. This bit is low when the data direction is into the local logic

and the FIFO is empty or when the data direction is out of the local

logic and the FIFO is full.

Bit 12-10:

This bit field indicates at which point the FIFO should issue a DMA

request. It is compared with the FIFO Data Quantity bit field to

determine when this should occur. Legal values are from

1 to 4. A value of zero causes no data transfers to occur. Values

greater than 4 are treated as 4.

Bit 9-8:

This bit field indicates which byte of the FIFO quad halfword structure

is the next to be used as output data.

Bit 7:

Not used

Bit 6:

This bit indicates that there is a full word in the holding register.

Bit 5:

This bit indicates that there is a single byte in the holding register.

Bit 4-2:

This bit field indicates the number of quad halfwords that contain data.

Valid values are from 0 to 4.

Bit 1-0:

This bit field indicates which byte of the FIFO quad halfword structure

is the next to receive input data.

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

USBEP1Data

(R/W)

$01FF858D

EP1 Bulkin Dataport Register

Reset Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

USBEP1Data

(R/W)

$01FF858C

EP1 Bulkin Dataport Register

Reset Value

00h

Read Value

00h

Bits 15-0:

Endpoint 1 FIFO Dataport Register

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

USBEP1Tran

(W)

$01FF858F

EP1 Transition Register

Reset. Value

xxh

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

USBEP1Tran

(W)

$01FF858E

EP1 Transition Register

Reset. Value

xxh

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