MFC2000 datasheet(300/426 Pages) ETC

300 / 426 page

MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

16-2

Conexant

100723A

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

USBEP1Fifo4

(R/W)

$01FF8587

EP1 Bulkin Half Word 4

Reset. Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

USBEP1Fifo4

(R/W)

$01FF8586

EP1 Bulkin Half Word 4

Reset. Value

00h

Read Value

00h

Bits 15-0:

Endpoint 1 FIFO Quad Half word 4

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

USBEP1Hold

(R/W)

$01FF8589

EP1 Bulkin Holding Register

Reset. Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

USBEP1Hold

(R/W)

$01FF8588

EP1 Bulkin Holding Register

Reset. Value

00h

Read Value

00h

Bits 15-0:

Endpoint 1 FIFO Quad Holding Register

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

USBEP1Ctrl

(R/W)

$01FF858B

Fifo Enabled

(Read Only)

Data

Request

(Read Only)

Fifo Ready

Fifo DMA Threshold

Fifo Output Pointer

Rst. Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

USBEP1Ctrl

(R/W)

$01FF858A

unused

Holding Reg

Full

Byte Present Fifo Data Quantity

Fifo Input Pointer

Rst. Value

x0000000b

Read Value

00h

Bit 15:

This bit indicates that the FIFO is active and capable of generating

DMA requests. This bit generally follows the setting of the LCL_ENB

input signal except the FIFO Enabled register bit will remain asserted

if the LCL_ENB input signal is set to false while the FIFO is executing

a DMA transfer. In this case, the register bit will remain set for the

duration of the DMA transfer and then become cleared.

Bit 14:

This bit is similar to the DMA_REQ signal except that it is not blocked

when DMA_TC0 is set. It indicates that the programmed threshold has

been met or exceeded and that the FIFO requires data transfers either

by enabling hardware DMA through DMA_TC0 or by executing

software DMA cycles.

MFC2000 Datasheet(PDF) 300 Page - List of Unclassifed Manufacturers

MFC2000 Datasheet(HTML) 300 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL