MFC2000 datasheet(296/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

15-16

Conexant

100723A

15.4 Firmware Operation

15.4.1 SASIF SyncMode Operation

SyncMode Setup

Set the SASSCLKDivisor Register for proper transmission rate.

Set the L2MSB bit for proper shifting order.

Set the SASSCLKPol bit for proper SASSCLK polarity.

Set the transmit FIFO or receiver FIFO to be enabled if lower system overhead or faster transfer rate is

required. By default, the two FIFO’s are disabled.

Clear the TxBufIrqEnb bit and/or the TxShfIrqEnb bit if continuous transmitting is not required (lower CPU

interrupt overhead and lower transfer rate), or set the TxBufIrqEnb bit and the TxShfIrqEnb bit if continuous

transmission is needed (higher CPU interrupt overhead and higher transfer rate).

Set the SASMode bit to select SyncMode operations.

Note: Steps 1 through 5 can be done in a setup-table load.

Data Transmit and Receive Example – FIFO mode disabled

Case when the TxBufIRQ and the TxShfIRQ are enabled:

The ARM writes first data to the SASData Register, and sets the TxBufIrqEnb and the TxShfIrqEnb bits.

The SASIF loads the TxBuffer Register (SASData Register ) to the TxShift Register and clears the

TxShfEmpty status bit.

The SASIF transmits, and receives bits 7 through bit 0 (if the L2MSB bit is cleared) or bit 0 through bit 7 (if the

L2MSB bit is set).

By the end of the step 3 data shifting, the ARM gets the TxBufIRQ, which indicates that the TxBuffer is ready

for next transmit and the RxBuffer is full.

The ARM reads the SASData Register for the RxBuffer Register data, and clears the TxBufIRQ by writing to

the TxBuffer Register with the next data. If no more data, the ARM clears the TxBufIrqEnb bit. If only transmit

is desired, the ARM can ignore the data in the RxBuffer Register.

If the TxBufEmpty status bit is cleared at the end of the data shifting, the SASIF will set the TxBufEmpty bit

and goto step 2. However, if the TxBufEmpty bit is set, the SASIF will set the TxShfEmpty status bit and

generates the TxShfIRQ.

The ARM gets the TxShfIRQ, which indicates the end of all data shifting. If no data is wished to be sent or

received, the ARM can then clear the TxShfIrqEnb bit.

Data Transmit and Receive Example – FIFO mode (both FIFO’s enabled)

Case when the TxBufIRQ and the TxShfIRQ are enabled:

Note: When using FIFO mode in synchonous mode, both FIFO’s must be enabled. This ensures

that the RxFIFO will contain the same number of bytes of data by the time the TxBufIRQ occurs

that were originally written to the TxFIFO. Otherwise, since only Tx interrupts are used, it will be

impossible to grab the received data if no received FIFO is used, and data will be lost if no

TxFIFO is used when an RxFIFO is used.

The ARM writes first data to the SASData Register up to sixteen times in a row, filling up the TxFIFO as much

as desired, and sets the TxBufIrqEnb and the TxShfIrqEnb bits.

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