MFC2000 datasheet(294/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

15-14

Conexant

100723A

Start

LSB

Stop

Wr SerData

SASTXD

SASSCLK

SASCs

TxBufEmpty

TxShfEmpty

Figure 15-4. Asynchronous Transmitter Timing

The bit capture timing above is identical whether FIFO mode is enabled or disabled. At the end of each

transmitted byte, a new byte will be loaded from the TxBuffer Register when FIFO mode is disabled, or from the

oldest valid location with the FIFO when FIFO mode is enabled. Following are the timing sequence for the

interrupt control and byte loading control for both FIFO enabled and FIFO disabled modes:

SASCSn

SASTXD

TxFIFOEnb

Txload

TxBufEmpty

TxShfEmpty

SAS DATA WR

15 16

bytes

Figure 15-5. Asynchronous Transmitter byte Timing



FIFO Mode Enabled

15.3.3.1 Asynchronous Mode Receiver Timing

Once AsyncMode is set, the receiver logic will look for a falling edge in the SASRXD signal and will stay in the

receiver idle state. While SASRXD stays high, the receiver idles. When the Start bit comes, the SASIF

EdgeDetector is triggered by the falling edge. Until the next internal 8X baud rate clock arrives, the beginning of

this character is defined. Each bit has 8 8X baud rate clock pulses in it. Data is sampled on the fourth Baud8X

clock from the receiving bit boundary. See Figure 15-6.

If the sampling value of the Start bit is a logic 1, that start bit is regarded as a glitch or an invalid character, no

RxBufIRQ will be generated.

Start bit

Sampling

LSB

Baud8X

SASRXD

Figure 15-6. Asynchronous Receiver Bit Timing

MFC2000 Datasheet(PDF) 294 Page - List of Unclassifed Manufacturers

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