MFC2000 datasheet(292/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

15-12

Conexant

100723A

15.3 SASIF Timing

15.3.1 SASSCLK Timing

When SASSCLK is on (Figure 15-2), the duty cycle of SASSCLK is always 50%.

Tserd

Tserd applies to SASSCLK, SASTXD, and

SASRXD

when they are in output configuration

AUXCLK

SASSCLK

SASTXD

SASRXD

Figure 15-2. SASSCLK Timing Diagram

In Figure 15-2, TSERd is the AUXCLK to SASSCLK, SASRXD and SASTXD delay. TSERd applies to SASSCLK,

SASTXD, and SASRXD when they are in output configuration.

The SASSCLK polarity is controlled by the SAS Command Register SASSCLKPol Bit. When the SASSCLKPol bit

is cleared (default), the SASTXD signal transition is on the SASSCLK falling edge. External logic can latch the

SASTXD signal on the SASSCLK rising edge. When the SASSCLKPol bit is set, the SASTXD signal transition is

on the rising edge of the SASSCLK. External logic can latch the SASTXD signal on the SASSCLK falling edge.

When configured in the SyncMode, the SASSCLK will be active for eight cycles for each write to the empty

SASData Register. Continuous SASSCLK can be achieved by keeping the transmit buffer register full. When

there is no data on the SASTXD pin, the SASSCLK will stay in idle state, which is logic zero as the SASSCLKPol

bit is clear and logic one as the SASSCLKPol bit is set. When configured in the AsyncMode, the SASSCLK is a

free running signal at the SASSCLKDivisor pre-defined clock rate.

15.3.2 Synchronous Mode Timing

When the SASIF is configured to the SyncMode, the SASIF generates the SASSCLK signal to synchronize data

transmit and receive. Therefore, only the transmitter related status bit and IRQ signals are used, and the

RxBufFull status bit and the RxBufIRQ signal are not used.

15.3.2.1 FIFOs Disabled

The TxBufEmpty and TxShfEmpty status bits are both set on system reset. When the FIFOs are disabled and

both the TxBuffer and TxShift Register are empty, writing to the SASData Register will clear the TxShfEmpty

status bit, and will fill the TxShift Register with the TxBuffer Register content.

When the TxBuffer is empty and the TxShift Register is non-empty, writing to the TxBuffer Register will clear the

TxBufEmpty status bit, and the TxShift Register is unaffected.

When the TxBuffer is full and the TxShift Register is empty, the TxBuffer Register value will be loaded into the

TxShift Register. The TxBufEmpty status bit will be set, and the TxShfEmpty flag is unaffected.

MFC2000 Datasheet(PDF) 292 Page - List of Unclassifed Manufacturers