MFC2000 datasheet(290/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

15-10

Conexant

100723A

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

SASDiv

01FF80F5

SASRXD

Early

1 - Early

(Not Used)

SASSCLK Divisor Upper Bits (13-8)

Rst. Value

0x000000b

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

SASDiv

01FF80F4

SASSCLK Divisor Lower Bits (7-0)

Rst. Value

00h

Read Value

00h

Bit 15:

SASRXDEarly (Receive Data Early)

Read/Write Bit.

If this bit is set to one (default = 0), the input data will be sampled 1/2

shift clock early from what is illustrated in Figure 15-2. This is only for

the sync mode.

Bit 14:

Not used

Bit 13-8:

DivHi (Divisor High Register)

Read/Write bits.

The DivHi Register is the higher bits (bit 13-8) of the SASSCLKDivisor

Bit 7-0:

DivLo (Divisor Low Register)

Read/Write bits.

The DivLo Register is the lower bits (bit 7-0) of the SASSCLKDivisor

internal counter. Firmware can transmit data with the right speed

immediately after the SASSCLK setup.

The SASSCLK Divisor Register defines the SASSCLK frequency, which depends on the AUXCLK frequency

(fTstClk). The SASSCLKDivisor Register has a fourteen bit divisor region. The SASSCLK frequency (fSClk)and

Divisor relationship is:

For the sync mode,

fINT

Divisor

SClk

AUXCLK

(

)

For the async mode,

fINT

Divisor

SClk

AUXCLK

(

)

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