MFC2000 datasheet(287/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

15-7

Bit 9:

RxFifoFull(Receive FIFO full)

Read only bit.

This bit goes high when the receive FIFO is completely full. New

received data received from the RxShiftReg will be thrown away. This

will not cause an interrupt, but the RxFifoThresh should have already

done so.

Bit 8:

RxFifoEmpty(Receive FIFO empty)

Read only bit.

This bit goes high when the receive FIFO is completely empty. This

will not cause an interrupt. This can be helpful in trying to figure out if

more data can be read from the receive FIFO.

Bit 7:

RxTimoutElapsed (Receive FIFO Timeout occurred)

Read only bit.

The RxTimoutElapsed shows the status of the Timeout function of the

receive FIFO. When the RxTimoutElapsed is set, the Timer has timed

out which means that the FIFO has not received any new data for too

long of a time, but the FIFO is not full. When this bit is cleared, the

receive FIFO is running properly. This will cause an interrupt in

conjunction with RxTimeoutEnb

Bit 6:

RxTimeoutEnb (Receive Timeout Interrupt Enable)

Read/Write bit.

When the RxTimerEnb is cleared (default), the RxTimeoutIRQ signal

will be disabled. When the RxTimerEnb bit is set, the RxTimeoutIRQ

will be enabled.

Bit 5:

TxBufEmpty/TxFifoThresh (Transmit Data Buffer Register Empty or Transmit FIFO Threshhold

met)

Read only bit.

The TxBufEmpty bit shows the status of the transmit buffer register

when TxFIFO is disabled. The transmit buffer register is empty when

this bit is set. The transmit buffer register is when this bit is cleared.

When TxFIFO is enabled, the transmit FIFO has met its threshhold

limit when this bit is set, and is not yet emptied to its threshhold when

this bit is cleared. This bit will cause an interrupt in conjunction with

TxBufIRQEnb.

Bit 4:

TxShfEmpty (Transmit Shift Data Register Empty)

Read only bit.

The TxShfEmpty bit shows the status of the transmit shift register. The

transmit shift register is empty when this bit is set. The transmit shift

Bit 3:

RxBufFull/RxFifoThresh (Receive Buffer Register Full or Receive FIFO Threshhold met)

Read only

bit.

The RxBufFull bit show the status of the receive buffer register (when

RxFIFO is disabled). The receive buffer register is empty when this bit

is cleared. The receive buffer register is when this bit is set. When

RxFIFO is enabled, the receive FIFO has met its threshhold when this

bit is set, and is not yet filled to its threshhold limit when this bit is

cleared. This bit will cause an interrupt in conjunction with

RxBufIRQEnb.

MFC2000 Datasheet(PDF) 287 Page - List of Unclassifed Manufacturers

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