MFC2000 datasheet(283/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

15-3

15.2 Register Description

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

SASCmd

01FF80F1

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

SASCmd

01FF80F0

(Not Used)

TxFIFOEnb

RxFIFOEnb

L2MSB

SASSCLKPo

DataLen

SASMode

Rst. Value

X0000000b

Read Value

00h

Bit 15-7:

Not used

Bit 6:

TxFIFOEnb

Read/Write bit.

This bit controls whether or not the 16-byte transmit FIFO is to be

used. When the TxFIFOEnb is cleared (default), the transmit FIFO will

not be used and an interrupt will be generated each time a byte is

sent. If TxFIFOEnb is set, the transmit FIFO will be used and an

interrupt will be generated only when the FIFO is completely emptied.

This should ONLY be written to during setup and not after the SASIF

has started sending or receiving data, as data loss could occur.

Bit 5:

RxFIFOEnb

Read/Write bit.

This bit controls whether or not the 16-byte receive FIFO is to be used.

When the RxFIFOEnb is cleared (default), the receive FIFO will not be

used and an interrupt will be generated for each byte received. If

RxFIFOEnb is set, then the receive FIFO will be used and an interrupt

will only be generated if the FIFO is full or a receive FIFO timeout

occurs. This should ONLY be written to during setup and not after the

SASIF has started sending or receiving data, as data loss could occur.

Bit 4:

L2MSB

Read/Write bit.

This bit controls the shifting order of the transmit and receive registers.

When the L2MSB bit is cleared (default) and the SASIF is set to the

AsyncMode or SyncMode, the transmit and receive shift register will

shift from the MSB to the LSB. When the L2MSB bit is set, the

transmit and receive register will shift from the LSB to MSB.

Bit 3:

SASSCLKPol

Read/Write bit.

This bit controls the polarity of the SASSCLK pin for the sync mode.

When the SASSCLKPol bit is cleared (default) and the SASIF is set to

AsyncMode or SyncMode, the SASSCLK polarity will be non-inverted,

which will enable the external logic to clock the SASTXD pin on the

rising edge of the SASSCLK pin. When the SASSCLKPol bit is set and

the SASIF is set to AsyncMode or SyncMode, the SASSCLK polarity

will be inverted, which will enable the external logic to clock the

SASTXD pin on the falling edge of the SASSCLK pin.

Bit 2:

DataLen

Read/Write bit.

This bit controls the number of bit for AsyncMode transmit. This bit is

not effective for the SyncMode. When the DataLen is cleared (default)

and the SASIF is set to the AsyncMode, the TxBuffer register bit 7 will

be the MSB and bit 0 will be the LSB for asynchronous transmit. The

transmit shifting order is controlled by the L2MSB bit. When the

DataLen is set and the SASIF is set to the AsyncMode, the TxBuffer

asynchronous transmit.

MFC2000 Datasheet(PDF) 283 Page - List of Unclassifed Manufacturers

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