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MFC2000 Datasheet(PDF) 285 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 285 Page - List of Unclassifed Manufacturers |
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285 / 426 page ![]() Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 15-5 Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: SASFifoPtr 01FF80F7 Tx Input Pointer Tx Output Pointer Rst. Value 00h Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: SASFifoPtr 01FF80F6 Rx Input Pointer Rx Output Pointer Rst. Value 00h Read Value 00h Register Description: SASIF Fifo Pointer Register Bit 15-12: Transmit FIFO input pointer (Read Only bit) Bit 11-8: Transmit FIFO output pointer (Read Only bit) Bit 7-4: Receiver FIFO input pointer (Read Only bit) Bit 3-0: Receiver FIFO output pointer (Read Only bit) Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: SASFifoQty 01FF80FD (Not Used) Tx FIFO Quantity TxFIFOThreshVal Rst. Value X0000011b Read Value 00000011b Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: SASFifoQty 01FF80FC (Not Used) Rx FIFO Quantity RxFIFOThreshVal Rst. Value X0000011b Read Value 00000011h Register Description: SASFifoQty Register Bit 15: Not Used Bit 14-10: TxFIFOQty (Transmit FIFO Quantity) Read Only bits. These five bits hold the value of the amount of bytes stored within the transmit FIFO. As data is written to or removed from the TxFIFO, the quantity will be adjusted accordingly. Bit 9-8: TxFIFOThreshVal (Transmit FIFO Threshhold value) Read/Write bits. Depending on how these two bits are set, will affect when the transmit FIFO considers itself empty enough to cause an interrupt. Bit Value # of bytes left in TxFIFO which should cause interrupt “00” 12 “01” 8 “10” 4 “11” 2 Bit 7: Not Used |
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