| Electronic Components Datasheet Search |
|
MFC2000 Datasheet(PDF) 284 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
MFC2000 Datasheet(HTML) 284 Page - List of Unclassifed Manufacturers |
|
284 / 426 page ![]() MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 15-4 Conexant 100723A Bit1-0: SASMode Read/Write bits. These two bits control the SASIF operation modes. 00: AsyncMode (default) 01: SyncMode 10 & 11: Reserved Note: The TxFIFO enable and the RxFIFO enable should either be set or cleared once in the setup of the SASIF device. Enabling or disabling the FIFOs once the MFC is up and running could have unpredicted results if data is being received or sent by the shift registers. Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: SASRxData 01FF80F3 (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) Rst. Value xxh Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: SASRxData 01FF80F2 SASRx Data(7) SASRx Data(6) SASRx Data(5) SASRx Data(4) SASRx Data(3) SASRx Data(2) SASRx Data(1) SASRx Data(0) Rst. Value 00h Read Value 00h Register Description: SASIF Rx Data Buffer Register Note: This is the Receive buffer data register. Reading from this register will return the data in the Rxbuffer (for fifo disabled) or the oldest valid received data (for fifo enabled). However, after a read, a write MUST be done to this register in order to let the SASIF know that data has been read. This was done to help with emulation testing. Writing to the SASData Register will clear the RxBufFull or RxFifoThresh status bits. Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: SASTxData 01FF80FB (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) Rst. Value xxh Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: SASTxData 01FF80FA SASTx Data(7) SASTx Data(6) SASTx Data(5) SASTx Data(4) SASTx Data(3) SASTx Data(2) SASTx Data(1) SASTx Data(0) Rst. Value 00h Read Value 00h Register Description: SASIF Tx Data Buffer Register (write only) Note: This is the Transmit buffer data register. It is a write only register. Writing to this register placed data into the transmit buffer register (or the transmit fifo if TxFifo is enabled). Writing to the SASTxData Register will clear the TxBufEmpty or TxFifoThresh status bits. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |