MFC2000 datasheet(281/426 Pages) ETC

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Multifunctional Peripheral Controller 2000

MFC2000

100723A

Conexant

15-1

15. Synchronous/Asynchronous Serial Interface (SASif)

15.1 Functional Description

The SASIF is a Synchronous/Asynchronous Receiver/Transmitter which performs serial-parallel conversion on

data received from a peripheral device, and parallel-to-serial conversion of data for transmission to a peripheral

device. The interface consists of serial transmit data (SASTXD), serial receive data (SASRXD), and a serial clock

(SASSCLK) signals. Figure 15-1 is a block diagram of the SASIF.

The SASIF includes a programmable baud rate generator for asynchronous and synchronous operations. Four

interrupts can be generated for the ARM. These are Transmit Shift Register empty, Transmit Buffer Register

Empty, or Receive Buffer Register full, and Receive FIFO Timeout. These interrupts can each be uniquely

enabled or disabled.

The SASIF can also be set to FIFO mode. In this mode, the ARM will be relieved of excessive interrupt handling

and will allow for an overall faster transmit and receive speed. A FIFO mode can be enabled for either the receive

portion or the transmit portion of the SASIF. When the transmit FIFO is enabled, a 16-byte FIFO will be used to

hold up to 16 bytes of data to be transmitted. The Transmit Buffer Empty interrupt will only be generated if the

transmit FIFO has no new data to transmit (it is empty). When the receive FIFO is enabled, a 16-byte FIFO will be

used to store up to 16 bytes of data which are received from the receive shift register. The Receive Buffer Full

interrupt will only be generated if the receive FIFO has no room left for incoming data (it is full).

The receive FIFO also includes a timeout function. If the receive FIFO is not full, but the last newly received byte

was longer than four byte times ago (based on the programmed baud rate), then a timeout interrupt will be

generated. A “byte time” is the time in which it takes to receive one byte of data.

The receive and transmit data is double buffered to provide more time for the ARM to process receive data. The

data shifting order, MSB to LSB or LSB to MSB, and the SASCLK polarity are programmable.

The synchronous communication mode enables the ARM to transmit and receive data synchronous referencing to

the serial clock.

The ARM can read the status of the SASIF at any time during operation. Status includes IRQ source (SASTXD or

SASRXD) and operation mode (synchronous or asynchronous). During the Input/Output mode the SASTXD,

SASRXD, and SASSCLK values can also be read or written by the ARM. The contents of each byte within the

transmit and receive fifo can be read any time during operation, as well as the input and output pointers to both

fifos.

Following is the feature summary of the Serial Interface:

•

Full duplex, three wire system: SASSCLK (serial clock), SASTXD (Transmit data), SASRXD (Receive data)

•

Independent transmit data shift register and receive data shift register

•

Double buffered receive and transmit data register

•

Programmable 7 or 8 data bit asynchronous serial-interface with a start bit, a stop bit and no parity

•

8 data bit synchronous serial-interface with programmable data shifting order

•

Programmable baud rate generator supports up to 14400 baud asynchronous transmit and receive (when in

fifo mode is not on), and up to 2 ICLK synchronous transmit and receive

•

Supports up to 115.2 Kbaud asynchronous transmit and receive when in FIFO mode

•

Single interrupt generation for Transmit Data Shift Register empty, Transmit Data Buffer Register empty,

Receive Data Buffer Register full, and Receive FIFO Timeout

•

In the FIFO mode, transmitter and receiver are each buffered with 16 byte FIFO’s to reduce the number of

interrupts to the ARM.

•

Maximum

±1% SASTXD Async transmit baud rate error

•

Maximum

±2.5% SASRXD Async receive baud rate allowable error

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