MFC2000 datasheet(293/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

15-13

When both the TxBuffer Register and TxShift register are empty, the TxShfEmpty status bit will be set when the

last bit of the data is shifted to the SASTXD pin.

15.3.2.2 FIFOs Enabled

When FIFOs are enabled and the transmit FIFO is completely empty and TxShift Register is empty, writing to the

SASData Register will clear the TxShfEmpty status bit, keep the TxBufEmpty bit set and will fill the TxShift

When the transmit FIFO is completely empty and the TxShift Register is non-empty, writing to the transmit FIFO

(accomplished by writing SASData) will clear the TxBufEmpty status bit and the TxShift Register is unaffected (it

will stay filled and the TxShfEnpty will stay cleared).

When the transmit FIFO is not empty and the TxShift Register is empty, the value of the oldest valid FIFO location

will be loaded into the TxShift Register. The TxBufEmpty status bit will be set only if the last valid FIFO location

was just transferred to the TxShift Register. The TxShfEmpty flag is unaffected.

When the transmit FIFO is completely empty and TxShift register are empty, the TxShfEmpty status bit will be set

when the last bit of the data is shifted to the SASTXD pin.

15.3.2.3 Transmiting and Sampling

The SASRXD signal is sampled on the falling edge of the SASSCLK when the SASSCLKPol bit is cleared.

SASRXD signal is sampled on the rising edge of the SASSCLK when the SASSCLKPol bit is set. If the

SASRXDEarly bit is set the SASRXD signal will be sampled 1/2 SASSCLK early.

When the L2MSB control bit is cleared, the MSB to the LSB of the TxShift Register will be shifted to the SASTXD

pin, and the SASRXD signal will be shifted into the MSB of the RxShift Register. If the L2MSB bit is set, the LSB

to the MSB of the TxShift Register will be shifted to the SASTXD pin, and the SASRXD signal will be shift into the

LSB of the RxShift Register. The DataLen bit is not used in the SyncMode, eight data bits will be transmitted or

received regardless of setting.

MSB

LSB

Wr SerData

D5 D4

D3 D2

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB

SASSCLK

SASTXD

SASRXD

SASCs

TxBufEmpty

TxShfEmpty

Figure 15-3. Synchronous Mode Timing

15.3.3 Asynchronous Mode Transmitter Timing

Once AsyncMode is set, the transmitter logic will set SASTXD to logic one and will stay in the transmitter idle

state. After the ARM writes to the SASData Register, SASTXD will output the Start bit (logic 0) on the next

SASSCLK falling edge. Starting from LSB of the TxShift Register (when L2MSB is set), a total of 7 or 8 bits of

data (depending on the DataLen bit) will be sent. The bit next to the last data bit is the Stop bit. Similarly to the

SyncMode transmit timing, the TxBufEmpty, TxShfEmpty status bits, and the TxBufIRQ, TxShfIRQ has the same

timing sequence. See Figure 15-4.

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