MFC2000 datasheet(337/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

17-15

Input data FIFO Control Register for the data from the external memory (the Reverse direction)

(for DMA channel 12):

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Parallel Port Input

Data FIFO Control

(PIOInFIFOCtrl)

$01FF823B

FIFO

Enabled

(R)

Data

Request

(R)

FIFO

Ready

(R)

FIFO DMA Threshold

FIFO Output Pointer

Rst Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Parallel Port Input

Data FIFO Control

(PIOInFIFOCtrl)

$01FF823A

(Not Used)

Holding

Byte Present FIFO Data Quantity

FIFO Input Pointer

Rst Value

x0000000b

Read Value

00h

Bit 15:

This bit indicates that the FIFO is active and capable of generating

DMA requests. This bit generally follows the setting of the LCL_ENB

input signal except the FIFO Enabled register bit will remain asserted

if the LCL_ENB input signal is set to false while the FIFO is executing

a DMA transfer. In this case, the register bit will remain set for the

duration of the DMA transfer and then become cleared.

Bit 14:

This bit is similar to the DMA_REQ signal except that it is not blocked

when DMA_TC0 is set. It indicates that the programmed threshold has

been met or exceeded and that the FIFO requires data transfers either

by enabling hardware DMA through DMA_TC0 or by executing

software DMA cycles.

Bit 13:

This bit indicates that the FIFO can accept data transfers to/from the

local logic. This bit is low when the data direction is into the local logic

and the FIFO is empty or when the data direction is out of the local

logic and the FIFO is full.

Bit 12-10:

This bit field indicates at which point the FIFO should issue a DMA

request. It is compared with the FIFO Data Quantity bit field to

determine when this should occur. Legal values are from 1 to 4. A

value of zero causes no data transfers to occur. Values greater than 4

are treated as 4.

Bit 9-8:

This bit field indicates which byte of the FIFO quad halfword structure

is the next to be used as output data.

Bit 7:

Not used

Bit 6:

This bit indicates that there is a full word in the holding register.

Bit 5:

This bit indicates that there is a single byte in the holding register.

Bit 4-2:

This bit field indicates the number of quad halfwords that contain data.

Valid values are from 0 to 4.

Bit 1-0:

This bit field indicates which byte of the FIFO quad halfword structure

is the next to receive input data.

Note: It is strongly recommended that the FIFO be disabled before firmware writes to the FIFO

Control register. The FIFO Control register contains data that is essential to the FIFO’s

operation. If this data is changed while the FIFO is operating, unpredictable operation will result.

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