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MFC2000 Datasheet(PDF) 333 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 333 Page - List of Unclassifed Manufacturers |
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333 / 426 page  Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 17-11 Interrupt Mask Register Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Parallel Port Interrupt Mask. (PIOIRQMask) $01FF8211 (Not Used) DMARIRQ MASK DMAFIRQ MASK HTE MASK RDX MASK IVT MASK CRX MASK DRX MASK Rst. Value x0000000b Read Value 00h Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Parallel Port Interrupt Mask (PIOIRQMask) $01FF8210 INIL MASK INIH MASK AFDL MASK AFDH MASK STRL MASK STRH MASK SINL MASK SINH MASK Rst. Value 00h Read Value 00h The mask register will be used to enable the interrupts when writing one to each corresponding bit and disable the interrupts when writing zero to the corresponding bit. FIFO Interface Register Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Parallel Port FIFO Interface PIOFIFOIF 01FF8213 (Not Used) (Not Used) REVFIFO_ LCLCLEARI NG (RD) REVFIFO_ LCLFLUSHI NG (RD) REVFIFO_ LCLREQ (RD) FWDFIFO_ LCLCLEARI NG (RD) FWDFIFO_ LCLFLUSHI NG (RD) FWDFIFO_ LCLREQ (RD) Rst. Value xx000000b Read Value 00h Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Parallel Port FIFO Interface PIOFIFOIF 01FF8212 REVFIFO_ LCLCLR FWDFIFO_ LCLCLR FWDFIFO_ TC0EN FWDFIFO_ ENABLE FWDFIFO_ FLUSH REVFIFO_ TC0EN REVFIFO_ ENABLE REVFIFO_ FLUSH Rst. Value 00h Read Value 00h REVFIFO_FLUSH causes the reverse FIFO to execute a flush of its contents. REVFIFO_ENABLE enables the reverse FIFO operation. When false, any pending DMA requests are first completed before the reverse FIFO becomes disabled. REVFIFO_TC0EN When low it enables the reverse FIFO DMA operation. FWDFIFO_FLUSH causes the forward FIFO to execute a flush of its contents. FWDFIFO_ENABLE enables the forward FIFO operation. When false, any pending DMA requests are first completed before the forward FIFO becomes disabled. FWDFIFO_TC0ENA When low it enables the forward FIFO DMA operation. FWDFIFO_LCLCLR FWD FIFO local asynchronous clear except waits for any pending DMA requests to finish before reset. REVFIFO_LCLCLR REV FIFO local asynchronous clear except waits for any pending DMA requests to finish before reset. FWDFIFO_LCLREQ FWD FIFO local request is similar to dmareq but ignores dmaEq0 input. Used for firmware DMA as a status signal. FWDFIFO_LCLFLUSHING high when lclFlush is pulsed high and stays high until the FIFO is flushed. FWDFIFO_LCLCLEARING high when lclClr is pulsed and stays high until the clear can be done(no dmaReq). REVFIFO_LCLREQ REV FIFO local request is similar to dmareq but ignores dmaEq0 input. Used for firmware DMA as a status signal. REVFIFO_LCLFLUSHING high when lclFlush is pulsed high and stays high until the FIFO is flushed. REVFIFO_LCLCLEARING high when lclClr is pulsed and stays high until the clear can be done (no dmaReq). |
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