MFC2000 datasheet(329/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

17-7

NACK

ACKn

This status bit indicates the level driven on the ACKn output pin. This

bit is the FACK bit NOR’ed with the ACKn output from the PPI state

machine. Since FACK is cleared on reset, this bit will appear set on

reset. This is read-only status bit.

NSIN

SLCTINn

This status bit indicates the level read on the SLCTINn* input pin after

synchronization and optional digital filtering. This is a read-only status

bit.

NSTR

Strobe*

This status bit indicates the level read on the STROBE* input pin after

synchronization and optional digital filtering. This is a read-only status

bit.

NAFD

AUTOFDn

This status bit indicates the level read on the AUTOFDn input pin after

synchronization and optional digital filtering. This is a read-only status

bit.

NINI

INITn

This status bit indicates the level read on the INITn input after

synchronization and optional digital filtering. This is a read-only status

bit.

SNFL

FAULTn Status

This status bit indicates the level read on the FAULTn output pin. This

is a read-only status bit.

SSEL

SLCTOUT Status

This status bit indicated the level read on the SLCTOUT output pin.

This is a read-only status bit.

SPER

Paper Error Status

This status bit indicated the level read on the PE output pin. This is a

read-only status bit.

FRDA

Force Reverse Data Available

This bit controls the RDA status during Nibble Mode and Byte Mode

when DMA is not used.

Parallel Port Data Register

The parallel Port Data Register is a 9-bit read/write register that is used to control the parallel port data bus.

Reading this register provides the latched logic levels at PD7-0 and AUTOFDn pin. Data is latched on every high

to low transition of STROBEn (HostClk), when PDOE is clear in the Parallel Port Control Register. If PDOE is set,

the Parallel Port Data Register is frozen, and unaffected by the transitions on STROBEn. Reading this register

clears the FULL bit, and clears the PDMA request. This register should not be read while the PDMA channel is

enabled.

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Parallel Port Data

Reg.

(PIOData)

$01FF8205

(Not Used)

NCMD

Rst. Value

xxxxxxx0b

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Parallel Port

Data Reg.

(PIOData)

$01FF8204

DATA(7)

DATA(6)

DATA(5)

DATA(4)

DATA(3)

DATA(2)

DATA(1)

DATA(0)

Rst. Value

00h

Read Value

00h

DATA

Data

This field is an 8-bit read/write field. When used, DATA provides the

latched logic levels on PD7-0 when STROBEn (HostCLk) last

transmitted from high to low with PDOE clear. When written, the DATA

value defines the logic levels to be driven by the QP1700 when PD7-0

is enabled by the PDOE bit. The most significant bit of the DATA field

corresponds to PD7 and the least significant bit to PD0.

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