MFC2000 datasheet(328/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

17-6

Conexant

100723A

Parallel Port Interface Register

The Parallel Port Interface Register is a read/write register that contains eleven bits to control the parallel port

interface signals. Four read-only bits are used to read the logic level of host input pins, two read-only bits are

used to read the logic level on the BUSY and ACKn printer output pins, and five read/write bits control the logic

levels on the printer output pins. When hardware handshaking is enabled(mode 1,2,3) BUSY and ACKn are

controlled by the PPI state machine. When hardware handshaking is disabled (mode 0) and the PPI state

machine is idle BUSY and ACKn may be controlled by the software using the FBSY and FACK bits.

Note: NFLT,SEL,PERR and FBSY are arranged as register bits 0, 1, 2, and 3, respectively, to

correspond to their use as parallel data lines during nibble mode reverse data transfers.

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Parallel Port

Interface Reg.

(PIOIF)

$01FF8203

(Not Used)

FRDA

SPER

(R)

SSEL

(R)

SNFL

(R)

NINI

(R)

NAFD

(R)

NSTR

(R)

Rst. Value

x0000000b

Read Value

07h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Parallel Port

Interface Reg.

(PIOIF)

$01FF8202

NSIN

(R)

NACK

(R)

BUSY

(R)

FACK

FBSY

PERR

SEL

NFLT

Rst. Value

08h

Read Value

08h

NFLT

FAULTn

This bit controls the logic level driven on FAULTn output pin. Setting

NFLT drives a high level and clearing SEL drives a low level.

SEL

SLCTOUT

This controls the logic level driven on the SLCTOUT output pin.

Setting SEL drives a high level and clearing SEL drives a low level.

PERR

Paper Error

This bit controls the logic level driven on the PE output pin. Setting

PERR drives a high level and clearing PERR drives a low level.

FBSY

Force Busy

This bit force a high level to be driven on the BUSY output pin.

Normally this is done when hardware handshaking is disabled(mode

0), and the PPI state machine is idle. The FBSY bit is OR’ed with the

BUSY output from the PPI state machine before driving the BUSY

output pin. IF FBSY is set, then the BUSY output pin is forced high,

and the BUSY bit is read high. This bit is set on reset.

FACK

Force Ack

This bit forces a low level to be driven on the ACKn output pin.

Normally this is done when hardware handshaking is disabled (mode

0), and the PPI state machine is idle. The FACK bit is NOR’ed with the

ACKn output from the PPI state machine before driving the ACKn

output pin. If FACK is set, then the ACKn output pin is forced low, and

the NACK bit is to be read low.

BUSY

This status bit indicates the level driven on the BUSY output pin. This

bit is the FBSY bit OR’ed with BUSY output from the PPI state

machine. Since FBSY is set on reset, this bit will appear set on reset.

This is a read-only status bit.

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