MFC2000 datasheet(330/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

17-8

Conexant

100723A

NCMD

Command

When read, this bit provides the logic level of the AUTOFDn pin when

STROBEn (hostClk) transitioned from high to low with PDOE clear. If

set, AUTOFDn was latched high. If low, AUTOFDn was latched low.

This is a read-only data bit. Writing NCMD has no effect.

Parallel Port ACK Pulse Width Register

The Parallel Port ACK Pulse Width Register is an 8-bit read/write register that defines the pulse width of ACKn

during compatibility mode (MODE = 1), and setup timing relative to ACKn during reverse transfer modes

(MODE=4,4,6). The Parallel Port ACKn Pulse Width Register can be written and rewritten to program different

timing values as transitions are made to new transfer modes.

An ACKn pulse width can be programmed to be 0 to 255 IHSCLK periods wide. At 20MHZ, this allows software to

set pulse widths anywhere in the range of 0 to 12.75us. If ACKW is set to zero, no ACKn pulse is generated at the

end of compatibility mode cycles.

Setup timing relative to ACKn during reverse transfer modes can be programmed to be 1 to 256 IHSCLK periods.

During nibble or byte modes(MODE=4,5), ACKW defines the setup timing from nibble or byte data (event 8 or 15)

and the falling edge of ACKn (event 9), or from peripheral status (event 13) to the rising edge of ACKn (event 11).

During ECP reverse transfers (MODE = 6), ACKW defines the setup timing from reverse data (event 42) to the

falling edge of ACKn (event 43).

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Parallel Port ACK

Pulse Width Reg.

(PIOAckPW)

$01FF8207

(Not Used)

Rst. Value

xxh

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Parallel Port ACK

Pulse Width Reg.

(PIOAckPW)

$01FF8206

ACKW(7)

ACKW(6)

ACKW(5)

ACKW(4)

ACKW(3)

ACKW(2)

ACKW(1)

ACKW(0)

Rst. Value

00h

Read Value

00h

ACKW

ACKn Pulse Width

This 8 bit field defines the pulse width of ACKn during compatibility

mode transfers (MODE = 1), and the setup relationship relative to

ACKn during reverse transfer modes (MODE=4,5,6). A pulse width

from 0 to 255 IHSCLK periods can be programmed.

Parallel Port Reverse Data Status Register

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Parallel Port Reverse

Data Status Reg.

(PIORevDataSTS)

$01FF8209 (R)

(Not Used)

Rst. Value

xxh

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Parallel Port Reverse

Data Status Reg.

(PIORevDataSTS)

$01FF8208 (R)

RVDAT(7)

RVDAT(6)

RVDAT(5)

RVDAT(4)

RVDAT(3)

RVDAT(2)

RVDAT(1)

RVDAT(0)

Rst. Value

00h

Read Value

00h

REVD ATA Reverse Data

This 8-bit field is the status of the reverse data that was written into the

Parallel Port Data Register oppid[7:0]. This normally is needed only for

diagnostic purposes. This is a read-only status register.

MFC2000 Datasheet(PDF) 330 Page - List of Unclassifed Manufacturers

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