MFC2000 datasheet(327/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

17-5

PDOE

Parallel Data Output Enable

This bit performs two functions. It controls the state of the PD bus

three-state output drives, and it qualifies the latching of data from the

PD bus into the Parallel Port Data Register. When set, PDOE enables

the PD bus output pin drivers, and prevents data from being latched

into the Parallel Port Register.

Setting ABRT affects the operation of PDOE. IF ABRT is set,

SLCTINn (1284ACTIVE) must remain high to allow PDOE to be set or

remain set. If ABRT is set and SLCTINn (1284Active) goes low, PDOE

is cleared, and setting PDOE has no effect.

ABRT

Abort

This causes the PPI to use SLCTINn (1284Active) to detect when the

host suddenly aborts a reverse transfer and returns to compatibility

mode. If ABRT is set, a low level on SLCTINn (1284 Active) causes

PDOE to be cleared and the PD bus output drivers to be three-stated.

In fact, if ABRT is set and SLCTINn (1284Active) is low, setting PDOE

has no effect. This protection logic, as all internal logic, operates from

a synchronized and optionally digitally filtered SLCTINn (1284Active)

that is latched into the parallel Port Interface Register.

RLD

Run Length Decompression

This is a read-only status bit which indicates when run-length

decompression is taking place during ECP forward data transfers.

RLD is set when a run-length count is received and loaded into the

internal counter, and cleared when the last read of the Parallel Port

Data Register takes place. This bit can only be set when ECP with

RLE (mode 3) is enabled. If MODE is reprogrammed during a

decompression, decompression continues and RLD remains set until

the operation is completed. RLD is cleared when RST is issued.

FFULL

Forward Data Register Full

This is a read-only status bit that indicates when parallel port data

from the host is latched in the Parallel Port Data Register. FFULL is

cleared when the Parallel Port Data Register is read. When

handshaking and DMA is enabled, FFULL sets and clears as data is

latched and read during forward data transfers. FFULL is also cleared

when RST is issued.

RFULL

Reverse Data Register Full

This is a read-only status bits indicates when parallel port data to the

host is latched in the Parallel Port Data Register. RFULL is cleared

when the Parallel Port Data Register is sent. When handshaking and

DMA is enabled, RFULL sets and clears as data is latched and sent

during reverse data transfers. RFULL is also cleared when RST is

issued.

PPIRSTN Parallel port software reset

Active low resets all the state machines and is programmable using

this register bit. During the normal operation this bit needs to be set to

allow the state machine to start.

TRIZN

Tri-state output enable

Active low to enable tri-state input during the forward(PC to printer)

transfers.

MFC2000 Datasheet(PDF) 327 Page - List of Unclassifed Manufacturers

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