MFC2000 datasheet(324/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

17-2

Conexant

100723A

17.1.5 ECP Forward

Extended Capabilities Port (ECP) Mode provides an asynchronous, byte-wide, bi-directional channel. The data

can be received by DMA mode or CPU mode as described in the Compatibility Mode section. The ECP protocol

provides the Data and command cycles types in both forward and reverse directions. The MODE = 2 and 3 for the

forward mode with RLE . When MODE is set to 2, ECP mode hardware handshaking is enabled during forward

data transfers, without RLE support. When mode 2 is programmed, the PPI responds to a high to low transition on

STROBEn (HostClk), and automatically sets and clears the BUSY bit in the Parallel Port Interface Register and

the BUSY to handshake with the host.. MODE may be reprogrammed at any time, but if an ECP cycle is currently

in progress, it completes as normal.

17.1.6 ECP Reverse

After a successful Forward to Reverse phase switch, the ECP changes into the reverse phase in MODE = 6.

When the 1284 interface is idle, this is the desired mode of operation. This mode will allow the MFC2000 ASIC to

inform the host of incoming fax data. The ECP Reverse mode can operate under CPU interrupt driven control or

automated DMA control. In CPU control, the software writes the outgoing byte into the output buffer and then sets

ACKn low to send the data. After the host completes the data transfer, the ACKn is automatically set high and the

CPU is free to respond to any PPI interrupts that have been enabled or to initiate an additional data transfer if

needed. The handshake signals are INITn, PE, ACKn, AUTOFDn and BUSY.

17.1.7 The Non-standard Dribble Mode

The dribble mode was used for the slower PC before P1284 is standardized. Dribble mode is similar to ECP in

that the channel can be reversed without having to go through a negotiation phase to turn the channel around. It

sends two bits at a time on the nPeriphRequest and XFlag signals rather than using the PIO data bus. In this

respect, it is similar to nibble mode's data transfer phase in that it uses HostBusy and PtrClk to transfer each

portion of the data byte. The dribble mode can only operate under CPU interrupt-driven control (no DMA mode).

Note: This is not an IEEE-1284 mode but is useful to support certain product interfaces created

prior to the IEEE-1284 specification.

17.2 Additional Features

17.2.1 Filter

A digital filter is provided for incoming host control and data signals. SLCTINn, STROBEn, AUTOFDn, and INITn

are provided with digital filter circuits which are collectively controlled by software. IF DFIL =0, then no digital

filtering is selected.

Note that synchronization plus digital filtering adds up to four CLK periods of delay before a level change at one of

the host inputs appears in the Parallel Port Control Register, and five periods of delay before an output responds

to an input (e.g., before BUSY responds to STROBEn).

Likewise, synchronization and digital filtering of STROBEn affect the point at which ippid[7-0] and AUTOFDn are

latched into the parallel Port Data Register. Without a DFIL=3, ippid[7-0] and AUTOFDn are sampled an the fourth

rising edge of CLK after STROBEn is sampled. With digital filtering, ippid7-0 and AUTOFDn are sampled on the

fifth rising edge of CLK after STROBEn is sampled.

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