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SLG46121 Datasheet(PDF) 1 Page - Dialog Semiconductor |
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SLG46121 Datasheet(HTML) 1 Page - Dialog Semiconductor |
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1 / 98 page  Silego Technology, Inc. Rev 1.06 000-0046121--106 Revised October 11, 2017 GreenPAK Dual Supply Programmable Mixed-signal Matrix SLG46121 Block Diagram Features • Logic & Mixed Signal Circuits • Highly Versatile Macrocells • 1.8 V (±5%) to 5 V (±10%) VDD • 1.8 V (±5%) to 5 V (±10%) VDD2 (VDD2 ≤ VDD) • Operating Temperature Range: -40°C to 85°C • RoHS Compliant / Halogen-Free • Pb-Free 12-pin STQFN: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch Applications • Personal Computers and Servers • PC Peripherals • Consumer Electronics • Data Communications Equipment • Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO GPIO 2 3 4 7 8 9 10 GPI VDD 1 STQFN-12 (Top View) 5 6 11 12 3-bit LUT3_1 or DFF5 Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 12 GPIO Pin 11 VDD2 Pin 5 GPIO Pin 6 GPIO Pin 8 GPIO Pin 7 GND Pin 10 GPIO Pin 9 GPIO ACMP0 ACMP1 Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT1 2-bit LUT2_4 3-bit LUT3_5 3-bit LUT3_4 Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_0 or DFF4 2bit LUT2_3 or DFF3 2-bit LUT2_2 or DFF2 3-bit LUT3_8 or Pipe Delay 3-bit LUT3_2 or DFF6 3-bit LUT3_3 or DFF7 4-bit LUT4_1 or CNT3 4bit LUT4_0 or CNT2 3-bit LUT2_6 3-bit LUT3_7 Vref RC Oscillator FILTER_0/Prog. Delay Additional Combination Functions POR Bandgap INV_0 Additional Logic Functions |
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