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AD9782 Datasheet(PDF) 4 Page - Analog Devices

Part # AD9782
Description  12-Bit, 200 MSPS/500 MSPS TxDAC with 2 x /4 x /8 x Interpolation and Signal Processing
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9782 Datasheet(HTML) 4 Page - Analog Devices

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AD9782
Preliminary Technical Data
Rev. PrC | Page 4 of 52
AD9782–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, unless
otherwise noted
Parameter
Min
Typ
Max
Unit
RESOLUTION
12
Bits
DC Accuracy1
Integral Nonlinearity
1.5
LSB
Differential Nonlinearity
0.75
LSB
ANALOG OUTPUT
Offset Error
% of FSR
Gain Error (Without Internal Reference)
% of FSR
Gain Error (With Internal Reference)
% of FSR
Full-Scale Output Current2
10
20
mA
Output Compliance Range
–1.0
+1.0
V
Output Resistance
TBD
kΩ
Output Capacitance
3
pF
REFERENCE OUTPUT
Reference Voltage
1.14
1.20
1.26
V
Reference Output Current3
1
µA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance (Ext Reference Mode)
10
MΩ
Small Signal Bandwith
0.5
MHz
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
ppm of FSR/°C
Gain Drift (Without Internal Reference)
ppm of FSR/°C
Gain Drift (With Internal Reference)
ppm of FSR/°C
Reference Voltage Drift
ppm /°C
POWER SUPPLY
AVDD1, AVDD2
Voltage Range
3.1
3.3
3.5
V
Analog Supply Current (IAVDD1)
mA
Analog Supply Current (IAVDD2)
mA
IAVDD1 in SLEEP Mode
mA
ACVDD, ADVDD
Voltage Range
2.35
2.5
2.65
V
Analog Supply Current (IACVDD)
mA
Analog Supply Current (IADVDD)
mA
CLKVDD
Voltage Range
2.35
2.5
2.65
V
Clock Supply Current (ICLKVDD)
mA
DVDD
Voltage Range
2.35
2.5
2.65
V
Digital Supply Current (IDVDD)
mA
DRVDD
Voltage Range
2.35
2.5/3.3
3.5
V
Digital Supply Current (IDRVDD)
mA
Nominal Power Dissipation4
1.25
W
OPERATING RANGE
–40
+85
°C
1 Measured at IOUTA driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32× the IREF current.
3 Use an external amplifier to drive any external load.
4 Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4× Interpolation, fDAC/4 Modulation, Hilbert Off.



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