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AD9782 Datasheet(PDF) 1 Page - Analog Devices |
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AD9782 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 52 page  12-Bit, 200 MSPS/500 MSPS TxDAC+® with 2×/4×/8× Interpolation and Signal Processing Preliminary Technical Data AD9782 Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES 12-bit resolution, 200 MSPS input data rate Selectable 2×/4×/8× interpolation filters Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes Single or dual-channel signal processing Selectable image rejection Hilbert transform Flexible calibration engine Direct IF transmission features Serial control interface Versatile clock and data interface SFDR 90 dBc @10 MHz WCDMA ACLR = 80 dBc @ 40 MHz IF DNL = ±0.75 LSB INL = ±1.5 LSB 3.3 V compatible digital Interface On-chip 1.2 V reference 80-lead thermally enhanced TQFP package APPLICATIONS Digital quadrature modulation architectures Multicarrier WCDMA, GSM, TDMA, DCS, PCS, CDMA Systems PRODUCT DESCRIPTION The AD9782 is a 12-bit, high speed, CMOS DAC with 2×/4×/8× interpolation and signal processing features tuned for communications applications. It offers state of the art distortion and noise performance. The AD9782 was developed to meet the demanding performance requirements of multicarrier and third generation base stations. The selectable interpolation filters simplify interfacing to a variety of input data rates while also taking advantage of oversampling performance gains. The modulation modes allow convenient bandwidth placement and selectable sideband suppression. The flexible clock interface accepts a variety of input types such as 1 V p-p sine wave, CMOS, and LVPECL in single ended or differential mode. Internal dividers generate the required data rate interface clocks. The AD9782 provides a differential current output, supporting single-ended or differential applications; it provides a nominal full-scale current from 10 mA to 20 mA. The AD9782 is manufactured on an advanced low cost 0.25 µm CMOS process. FUNCTIONAL BLOCK DIAGRAM 16-BIT DAC ZERO STUFF HILBERT ∆t 0 90 0 90 0 90 2× 2× 2× LATCH 2× 2× 2× LATCH Q I fDAC/2 fDAC/4 fDAC/8 ×1 ×2 ×4 ×8 CLOCK DISTRIBUTION AND CONTROL CLK+ CLK– LPF DATACLK/ PLL_LOCK P2B[15:0] P1B[15:0] FSADJ REFIO IOUTA IOUTB SDIO SDO CSB SCLK RESET Figure 1. |
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