AD9782 datasheet(24/52 Pages) AD

24 / 52 page

AD9782

Preliminary Technical Data

Rev. PrC | Page 24 of 52

AD9782 CLOCK/DATA TIMING

DLL Disabled, Two-Port Data Mode, DATACLK as Output

With the interpolation set to 1×, the DATACLK output is a

delayed and inverted version of DACCLK at the same

frequency. Note that DACCLK refers to the differential clock

inputs applied at Pins 5 and 6. As Figure 37 shows, there is a

constant delay between the rising edge of DACCLK and the

falling edge of DATACLK.

The DCLKPOL bit (Reg 02 Bit 4) allows the data to be latched

into the AD9782 on either the rising or falling edge of

DACCLK. With DCLKPOL = 1, the data is latched in on the

rising edge of Diff Clk, as shown in Figure 37. With DCLKPOL

= 0, as shown in Figure 38, data is latched in on the falling edge

of DACCLK. The setup and hold times are always with respect

to the latched edge of DACCLK.

DACCLKIN

DATACLKOUT

DATA

t12

tD = 5ns TYP

tH = 2.9ns TYP

tS = –0.5ns TYP

Figure 37. Data Timing, DLL Off, 1× Interpolation, DCLKPOL = 1

DACCLKIN

DATACLKOUT

DATA

tD = 6ns TYP

tH = 2.9ns TYP

tS = –0.5ns TYP

Figure 38. Data Timing, DLL Off, 1× Interpolation, DCLKPOL = 0

AD9782 Datasheet(PDF) 24 Page - Analog Devices