AD9782 datasheet(18/52 Pages) AD

18 / 52 page

AD9782

Preliminary Technical Data

Rev. PrC | Page 18 of 52

MSB/LSB TRANSFERS

The AD9782 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by register address DATADIR

(00h[6]). The default is MSB first. When this bit is set active

high, the AD9782 serial port is in LSB first format. That is, if the

AD9782 is in LSB first mode, the instruction byte must be

written from least significant bit to most significant bit.

Multibyte data transfers in MSB format can be completed by

writing an instruction byte that includes the register address of

the most significant byte. In MSB first mode, the serial port

internal byte address generator decrements for each byte

required of the multibyte communication cycle. Multibyte data

transfers in LSB first format can be completed by writing an

instruction byte that includes the register address of the least

significant byte. In LSB first mode, the serial port internal byte

address generator increments for each byte required of the

multibyte communication cycle.

The AD9782 serial port controller address will increment from

1Fh to 00h for multibyte I/O operations if the MSB first mode is

active. The serial port controller address will decrement from

00h to 1Fh for multibyte I/O operations if the LSB first mode is

active.

NOTES ON SERIAL PORT OPERATION

The AD9782 serial port configuration bits reside in Bits 6 and 7

of register address 00h. It is important to note that the

configuration changes immediately upon writing to the last bit

of the register. For multibyte transfers, writing to this register

may occur during the middle of communication cycle. Care

must be taken to compensate for this new configuration for the

remaining bytes of the current communication cycle.

The same considerations apply to setting the software reset,

SWRST (00h[5]) bit. All other registers are set to their default

values but the software reset doesn’t affect the bits in register

address 00h and 04h.

It is recommended to use only single byte transfers when

changing serial port configurations or initiating a software

reset.

R/W N1

N0 A4A 3A

D7 D6N D5N

D00

D10

D20

D30

D7 D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 30. Serial Register Interface Timing MSB First

A3 A4

N1 R/W D00 D10 D20

D7N

D6N

D5N

D4N

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Figure 31. Serial Register Interface Timing LSB First

INSTRUCTION BIT 6

INSTRUCTION BIT 7

CSB

SCLK

SDIO

tDS

tDH

tPWH

tPWL

tSCLK

Figure 32. Timing Diagram for Register Write

DATA BIT n–1

DATA BIT n

CSB

SCLK

SDIO

SDO

tDV

Figure 33. Timing Diagram for Register Read

AD9782 Datasheet(PDF) 18 Page - Analog Devices

AD9782 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL