AD9782 datasheet(7/52 Pages) AD

7 / 52 page

Preliminary Technical Data

AD9782

Rev. PrC | Page 7 of 52

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80 79 78 77 76

71 70 69 68 67 66 65

75 74 73 72

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN 1

IDENTIFIER

NC = NO CONNECT

CLKVDD

LPF

CLKVDD

CLKGND

CLK+

CLK–

CLKGND

DGND

DVDD

P1B15

P1B14

P1B13

P1B12

P1B11

P1B10

DGND

DVDD

P1B9

P1B8

P1B7

FSADJ

REFIO

RESET

CSB

SCLK

SDIO

SDO

DGND

DVDD

P2B0

P2B1

P2B2

P2B3

P2B4

P2B5

DGND

AD9782

TOP VIEW

(Not to Scale)

DVDD

P2B6

P2B7

P2B8

Figure 2. Pin Configuration

CLOCK

Table 4. Clock Pin Function Descriptions

No.

Mnemonic

Direction

Description

5, 6

CLK+, CLK–

Differential Clock Input.

LPF

I/O

PLL Loop Filter.

PLOCKEXT

04h[0]

DCLKEXT

02h[3]

Mode

Pin configured for input of channel data rate or synchronizer clock.

Internal clock synchronizer may be turned on or off with DCLKCRC

(02h[2]).

Pin configured for output of channel data rate or synchronizer clock

DATACLK/PLL_LOCK

I/O

Internal Clock PLL Status Output:

0: Internal clock PLL is not locked.

1: Internal clock PLL is locked.

1, 3

CLKVDD

Clock Domain 2.5 V.

4, 7

CLKGND

Clock Domain 0 V.

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