AD9782 datasheet(20/52 Pages) AD

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AD9782

Preliminary Technical Data

Rev. PrC | Page 20 of 52

Table 13.

DATA(02)

Bit

Direction

Default

Description

DATAFMT

0: Twos complement data format

1: Unsigned binary input data format

ONEPORT

0: I and Q input data onto ports one and two respectively

1: I and Q input data interleaved onto port one

DCLKSTR

0: DATACLK pin 12 mA drive strength

1: DATACLK pin 24 mA drive strength

DCLKPOL

0: Input data latched on DATACLK rising edge

1: Input data latched on DATACLK falling edge

DCLKEXT

0: With PLOCKEXT off, DATACLK pin inputs channel data rate or modulator synchronizer clock

1: With PLOCKEXT off, DATACLK pin outputs channel data rate or modulator synchronizer clock

DCLKCRC

0: With PLOCKEXT off, and DATACLK pin as input, DATACLK clock recovery off

1: With PLOCKEXT off, and DATACLK pin as input, DATACLK clock recovery on

IQPOL

0: In one port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data into Q channel

1: In one port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data into Q channel

GRAYDIN

0: Gray decoder off

1: Gray decoder on

Table 14.

MODULATE(03)

Bit

Direction

Default

Description

MODDUAL

03h [5]

CHANNEL

03h[7]

I channel processing routed to DAC

Q channel processing routed to DAC

Modulator real output routed to DAC

CHANNEL

Modulator imaginary output routed to DAC

HILBERT

1: With MODDUAL on, Hilbert transform on

MODDUAL

0: Modulator uses a single channel

1: Modulator uses both I and Q channels

SIDEBAND

0: With MODDUAL on, lower sideband rejected

1: With MODDUAL on, upper sideband rejected

MOD[1:0]

[3:2]

00: No modulation

01: fS/2 modulation

10: fS /4 modulation

11: fS /8 modulation

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