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AD9782 Datasheet(PDF) 19 Page - Analog Devices

Part # AD9782
Description  12-Bit, 200 MSPS/500 MSPS TxDAC with 2 x /4 x /8 x Interpolation and Signal Processing
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9782 Datasheet(HTML) 19 Page - Analog Devices

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Preliminary Technical Data
AD9782
Rev. PrC | Page 19 of 52
MODE CONTROL (VIA SPI PORT)
Table 10.
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COMMS
00
SDIODIR
DATADIR
SWRST
SLEEP
PDN
PLLLOCK
EXREF
FILTER
01
INTERP[1]
INTERP[0]
ZSTUFF
HPFX8
HPFX4
HPFX2
DATA
02
DATAFMT
ONEPORT
DCLKSTR
DCLKPOL
DCLKEXT
DCLKCRC
IQPOL
CRAYDIN
MODULATE
03
CHANNEL
HILBERT
MODDUAL
SIDEBAND
MOD[1]
MOD[0]
PLL
04
PLLON
PLLMULT[1]
PLLMULT[0]
PLLDIV[1]
PLLDIV[0]
PLLAZ[1]
PLLAZ[0]
PLOCKEXT
DCLKCRC
05
DATADJ[3]
DATADJ[2]
DATADJ[1]
DATADJ[0]
MODSYNC
MODADJ[2]
MODADJ[1]
MODADJ[0]
06
Reserved
07
Reserved
08
Reserved
09
Reserved
0A
Reserved
0B
Reserved
0C
Reserved
VERSION
0D
VERSION[3]
VERSION[3]
VERSION[3]
VERSION[3]
CALMEMCK
0E
RESERVED
RESERVED
CALMEM[1]
CALMEN[0]
CALCKDIV[2]
CALCKDIV[2]
CALCKDIV[2]
MEMRDWR
0F
CALSTAT
CALEN
XFERSTAT
XFEREN
SMEMWR
SMEMRD
FMEMRD
UNCAL
MEMADDR
10
MEMADDR[7]
MEMADDR[6]
MEMADDR[5]
MEMADDR[4]
MEMADDR[3]
MEMADDR[2]
MEMADDR[1]
MEMADDR[0]
MEMDATA
11
MEMDATA[5]
MEMDATA[4]
MEMDATA[3]
MEMDATA[2]
MEMDATA[1]
MEMDATA[0]
DCRSTAT
12
DCRSTAT[2]
DCRSTAT[1]
DCRSTAT[0]
Table 11.
COMMS(00)
Bit
Direction
Default
Description
SDIODIR
7
I
0
0: SDIO pin configured for input only during data transfer
1: SDIO configured for input or output during data transfer
DATADIR
6
I
0
0: Serial data uses MSB first format
1: Serial data uses LSB first format
SWRST
5
I
0
1: Default all serial register bits, except addresses 00h and 04h
SLEEP
4
I
0
1: DAC output current off
PDN
3
I
0
1: All analog and digital circuitry, except serial interface, off
PLLOCK
1
O
0
0: With PLL on, indicates that PLL is not locked
1: With PLL on, indicates that PLL is locked
EXREF
0
I
0
0: Internal band gap reference
1: External reference
Table 12.
FILTER(01)
Bit
Direction
Default
Description
INTERP[1:0]
[7:6]
I
00
00: No interpolation
01: Interpolation 2×
10: Interpolation 4×
11: Interpolation 8×
ZSTUFF
3
I
0
1: Zero Stuffing on
HPFX8
2
I
0
0: ×8 interpolation filter configured for low pass
1: ×8 interpolation filter configured for high pass
HPFX4
1
I
0
0: ×4 interpolation filter configured for low pass
1: ×4 interpolation filter configured for high pass
HPFX2
0
I
0
0: ×2 interpolation filter configured for low pass
1: ×2 interpolation filter configured for high pass



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