AD9782 datasheet(21/52 Pages) AD

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Preliminary Technical Data

AD9782

Rev. PrC | Page 21 of 52

Table 15.

PLL(04)

Bit

Direction

Default

Description

PLLON

0: PLL off

1: PLL on

PLLMULTI[1:0]

[6:5]

PLL MULTIPLY FACTOR

00: ×2

00: ×4

00: ×8

00: ×16

PLLDIV[1:0]

[4:3]

PLLMULT rate divide factor

00:/1

00:/2

00:/4

00:/8

PLLAZBW[1:0]

[2:1]

PLL Autozero settling bandwidth as fraction of CLK ±rate

00: /8 (lowest)

01: /4

10: /2 (highest)

PLOCKEXT

0: With PLL on, DATACLK/PLL_LOCK pin configured for DATACLK input/output

1: With PLL on, DATACLK/PLL_LOCK pin configured for output of PLLLOCK

Table 16.

DCLKCRC(05)

Bit

Direction

Default

Description

DATADJ[3:0]

[7:4]

0000

DATACLK offset. Twos complement respresentation

0111: +7

0000: 0

1000: -8

MODSYNC

0: With PLOCKEXT off, channel data rate clock synchronizer mode

1: With PLOCKEXT off, state machine clock synchronizer mode

fS/8

fS/4

fS/2

000

001

1/√2

–1

010

–1

011

–1/√2

–1

100

–1

101

–1/√2

–1

110

–1

MODADJ[2:0]

[2:0]

000

111

1/√2

–1

Modulator coefficient offset

Table 17.

VERSION(0D)

Bit

Direction

Default

Description

VERSION[3:0]

[3:0]

–

Hardware version identifier

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