DS2153Q datasheet(7/52 Pages) DALLAS

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DS2153Q

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SYMBOL

TYPE

DESCRIPTION

TCHBLK

Transmit Channel Block. A user-programmable output that can be

forced high or low during any of the 32 E1 channels. Useful for

blocking clocks to a serial UART or LAPD controller in

applications where not all E1 channels are used, such as Fractional

E1, 384 kbps service (H0), 1920 kbps (H12), or ISDN-PRI. Also

useful

for

locating

individual

channels

drop-and-insert

applications. See Section 13 for timing details.

TLCLK

Transmit Link Clock. 4 kHz to 20 kHz demand clock for the

TLINK input; controlled by TCR2. See Section 13 for timing

details.

TLINK

Transmit Link Data. If enabled, this pin will be sampled on the

falling edge of TCLK to insert the Sa bits See Section 13 for timing

details.

TSYNC

I/O

Transmit Sync. A pulse at this pin will establish either frame or

multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q

can be programmed to output either a frame or multiframe pulse at

this pin. See Section 13 for timing details.

DVDD

Digital Positive Supply. 5.0 volts. Should be tied to RVDD and

TVDD pins.

TCLK

Transmit Clock. 2.048 MHz primary clock. Needed for proper

operation of the parallel control port.

TSER

Transmit Serial Data. Transmit NRZ serial data, sampled on the

falling edge of TCLK.

TCHCLK

Transmit Channel Clock. 256 kHz clock which pulses high during

the LSB of each channel. Useful for parallel to serial conversion of

channel data. See Section 13 for timing details.

AD0

AD1

AD2

AD3

I/O

Address/Data Bus. A 8-bit multiplexed address/data bus.

DS2153Q Datasheet(PDF) 7 Page - Dallas Semiconductor

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