DS2153Q datasheet(25/52 Pages) DALLAS

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DS2153Q

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on E1 lines running with CRC4 multiframe. These count registers will increment once each time the

received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter

cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will

continue to count if loss of multiframe sync occurs at the CAS level.

EBCR1: E-BIT COUNT REGISTER 1 (Address=04 Hex)

EBCR2: E-BIT COUNT REGISTER 2 (Address=05 Hex)

(MSB)

(LSB)

(note 1)

EB9

EB8

EBCR1

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

EBCR2

SYMBOL

POSITION

NAME AND DESCRIPTION

EB9

EBCR1.1

MSB of the 10-bit E-Bit count

EB0

EBCR2.0

LSB of the 10-bit E-Bit count

NOTES:

1. The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.

5.4 FAS Bit Error Counter

FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word

of a 12-bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is

disabled during loss of synchronization conditions, (RLOS = 1). Since the maximum FAS word error

count in a 1-second period is 4000, this counter cannot saturate.

FASCR1: FAS BIT COUNT REGISTER 1 (Address=02 Hex)

FASCR2: FAS BIT COUNT REGISTER 2 (Address=04 Hex)

(MSB)

(LSB)

FAS11

FAS10

FAS9

FAS8

FAS7

FAS6

(note 2)

FASCR1

FAS5

FAS4

FAS3

FAS2

FAS1

FAS0

(note 1)

FASCR2

SYMBOL

POSITION

NAME AND DESCRIPTION

FAS11

FASCR1.7

MSB of the 12-bit FAS error count

FAS0

FASCR2.2

LSB of the 12-bit FAS error count

NOTES:

1. The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error

counter.

2. The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-Bit counter.

6.0 Sa DATA LINK CONTROL AND OPERATION

The DS2153Q provides for access to the proposed E1 performance monitor data link in the Sa bit

positions. The device allows access to the Sa bits either via a set of two internal registers (RNAF and

TNAF) or via two external pins (RLINK and TLINK).

DS2153Q Datasheet(PDF) 25 Page - Dallas Semiconductor

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