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DS2153Q Datasheet(PDF) 40 Page - Dallas Semiconductor |
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DS2153Q Datasheet(HTML) 40 Page - Dallas Semiconductor |
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40 / 52 page ![]() DS2153Q 40 of 52 1.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13-3 NOTES: 1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to 1). 2. RSYNC is in the output mode (RCR1.5=0). 3. RSYNC is in the input mode (RCR1.5=1). 4. RCHBLK is programmed to block channel 24. 2.048 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13-4 NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). 3. RCHBLK is programmed to block channel 1. |
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