DS2153Q datasheet(14/52 Pages) DALLAS

14 / 52 page

DS2153Q

14 of 52

CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)

(MSB)

(LSB)

FLB

THDB3

TG802

TCRC4

RSM

RHDB3

RG802

RCRC4

SYMBOL

POSITION

NAME AND DESCRIPTION

FLB

CCR1.7

Framer Loopback.

0=loopback disabled

1=loopback enabled

THDB3

CCR1.6

Transmit HDB3 Enable.

0=HDB3 disabled

1=HDB3 enabled

TG802

CCR1.5

Transmit G.802 Enable. See Section 13 for details.

0=do not force TCHBLK high during bit 1 of timeslot 26

1=force TCHBLK high during bit 1 of timeslot 26

TCRC4

CCR1.4

Transmit CRC4 Enable.

0=CRC4 disabled

1=CRC4 enabled

RSM

CCR1.3

Receive Signaling Mode Select.

0=CAS signaling mode

1=CCS signaling mode

RHDB3

CCR1.2

Receive HDB3 Enable.

0=HDB3 disabled

1=HDB3 enabled

RG802

CCR1.1

Receive G.802 Enable. See Section 13 for details.

0=do not force RCHBLK high during bit 1 of timeslot 26

1=force RCHBLK high during bit 1 of timeslot 26

RCRC4

CCR1.0

Receive CRC4 Enable.

0=CRC4 disabled

1=CRC4 enabled

FRAMER LOOPBACK

When CCR1.7 is set to a 1, the DS2153Q will enter a Framer LoopBack (FLB) mode. This loopback is

useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side

back to the receive side. When FLB is enabled, the following will occur:

1. data will be transmitted as normal at TTIP and TRING

2. data off the E1 line at RTIP and RRING will be ignored

3. the RCLK output will be replaced with the TCLK input.

DS2153Q Datasheet(PDF) 14 Page - Dallas Semiconductor

DS2153Q Datasheet(HTML) 14 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL