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DS2153Q Datasheet(PDF) 33 Page - Dallas Semiconductor |
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DS2153Q Datasheet(HTML) 33 Page - Dallas Semiconductor |
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33 / 52 page ![]() DS2153Q 33 of 52 TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex) (MSB) (LSB) Si 00 11 0 1 1 SYMBOL POSITION NAME AND DESCRIPTION Si TAF.7 International Bit. 0 TAF.6 Frame Alignment Signal Bit. 0 TAF.5 Frame Alignment Signal Bit. 1 TAF.4 Frame Alignment Signal Bit. 1 TAF.3 Frame Alignment Signal Bit. 0 TAF.2 Frame Alignment Signal Bit. 1 TAF.1 Frame Alignment Signal Bit. 1 TAF.0 Frame Alignment Signal Bit. TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address=21 Hex) (MSB) (LSB) Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 SYMBOL POSITION NAME AND DESCRIPTION Si TNAF.7 International Bit. 1 TNAF.6 Frame Non-Alignment Signal Bit. A TNAF.5 Remote Alarm. Sa4 TNAF.4 Additional Bit 4. Sa5 TNAF.3 Additional Bit 5. Sa6 TNAF.2 Additional Bit 6. Sa7 TNAF.1 Additional Bit 7. Sa8 TNAF.0 Additional Bit 8. 12.0 LINE INTERFACE FUNCTIONS The line interface function in the DS2153Q contains three sections: (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR), which is described below. |
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