DS2153Q datasheet(35/52 Pages) DALLAS

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DS2153Q

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pin or from the crystal attached to the XTAL1 and XTAL2 pins. The DS2153Q will sense the ACLKI pin

to determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to RVSS

to prevent the device from falsely sensing a clock. See Table 12.1. If the jitter attenuator is either placed

in the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due

to the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive

path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50%

duty cycle. Please see the Receive AC Timing Characteristics in Section 14 for more details.

SOURCE OF RCLK UPON RCL Table 12-1

ACLKI PRESENT?

RECEIVE SIDE JITTER

ATTENUATOR

TRANSMIT SIDE JITTER

ATTENUATOR

yes

ACLKI via the jitter attenuator

ACLKI

centered crystal

TCLK via the jitter attenuator

12.2 Transmit Waveshaping and Line Driving

The DS2153Q uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter

(DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms created by the

DS2153Q meet the ITU specifications. See Figure 12.3. The user will select which waveform is to be

generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR). The

DS2153Q can set up in a number of various configurations depending on the application. See Table 12.2

and Figure 12.1.

LINE BUILD OUT SELECT IN LICR Table 12-2

APPLICATION

TRANSFORMER

RETURN LOSS

75-ohm normal

1:1.15 step-up

0 ohms

120-ohm normal

1:1.15 step-up

0 ohms

75-ohm normal with

protection resistors

1:1.15 step-up

8.2

ohms

120-ohm normal with

protection resistors

1:1.15 step-up

8.2

ohms

75-ohm with high return loss

1:1.15 step-up

21 dB

27 ohms

75-ohm with high return loss

1:1.36 step-up

21 dB

18 ohms

120-ohm with high return loss

1:1.36 step-up

21 dB

27 ohms

NM=Not Meaningful

Due to the nature of the design of the transmitter in the DS2153Q, very little jitter (less then 0.00 5UIpp

broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLK. Also, the waveforms that they

create are independent of the duty cycle of TCLK. The transmitter in the DS2153Q couples to the E1

transmit shielded twisted pair or COAX via a 1:1.15 or 1:1.36 step up transformer as shown in Figure

12.1. In order for the devices to create the proper waveforms, this transformer used must meet the

specifications listed in Table 12.3.

DS2153Q Datasheet(PDF) 35 Page - Dallas Semiconductor

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