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DS2153Q Datasheet(PDF) 36 Page - Dallas Semiconductor

Part # DS2153Q
Description  E1 Single-Chip Transceiver
PDF  52 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2153Q Datasheet(HTML) 36 Page - Dallas Semiconductor

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TRANSFORMER SPECIFICATIONS Table 12-3
SPECIFICATION
RECOMMENDED VALUE
Turns Ratio
1:1 (receive) and 1:1.15 or 1:1.36 (transmit)
±5%
Primary Inductance
600
µH minimum
Leakage Inductance
1.0
µH maximum
Interwinding Capacitance
60 pF maximum
DC Resistance
1.2 ohms maximum
12.3 Jitter Attenuator
The DS2153Q contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications.
The characteristics of the attenuation are shown in Figure 12.4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order
for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 12.4 below
must be connected to the XTAL1 and XTAL2 pins.
The jitter attenuator divides the clock provided by the 8.192 MHz crystal at the XTAL1 and XTAL2 pins
to create an output clock that contains very little jitter.
Onboard circuitry will pull the crystal (by
switching in or out load capacitance) to keep it long-term averaged to the same frequency as the incoming
E1 signal. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer
depth is 32 bits), then the DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the
normal 4 to keep the buffer from overflowing. When the device divides by either 3.5 or 4.5, it also sets
the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
CRYSTAL SPECIFICATIONS GUIDELINES Table 12-4
PARAMETER
SPECIFICATION
Parallel Resonant Frequency
8.192 MHz
Mode
Fundamental
Load Capacitance
18 pF to 20 pF (18.5 pF nominal)
Tolerance
±50 ppm
Pullability
CL=10 pF, delta frequency=+175 to +250 ppm
CL=45 pF, delta frequency=-175 to -250 ppm
Effective Series Resistance
30 ohms maximum
Crystal Cut
AT



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