DS2153Q datasheet(31/52 Pages) DALLAS

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DS2153Q

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NOTE:

If CCR3.6=1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER and a 1

implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS) registers.

See definition below.

TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1

(MSB)

(LSB)

CH20

CH4

CH19

CH3

CH18

CH2

CH17*

CH1*

TCBR1

CH24

CH8

CH23

CH7

CH22

CH6

CH21

CH5

TCBR2

CH28

CH12

CH27

CH11

CH26

CH10

CH25

CH9

TCBR3

CH32

CH16

CH31

CH15

CH30

CH14

CH29

CH13

TCBR4

* = CH1 and CH17 should be set to 1 to allow the internal TS1 register to create the CAS Multiframe

Alignment Word and Spare/Remote Alarm bits.

10.0 ELASTIC STORE OPERATION

The DS2153Q has an onboard two-frame (512 bits) elastic store. This elastic store can be enabled via

RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz

(RCR2.2=0) or 2.048 MHz (RCR2.2=1) clock at the SYSCLK pin. If the elastic store is enabled, then the

user has the option of either providing a frame sync at the RSYNC pin (RCR1.5=1) or having the

RSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.5=0). If the user wishes to obtain

pulses at the frame boundary, then RCR1.6 must be set to 0, and if the user wishes to have pulses occur at

the multiframe boundary, then RCR1.6 must be set to 1. If the user selects to apply a 1.544 MHz clock to

the SYSCLK pin, then every fourth channel will be deleted and the F-bit position inserted (forced to 1).

Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted.

Also, in 1.544 MHz applications, the RCHBLK output will not be active in channels 25 through 32 (or in

other words, RCBR4 is not active). See Section 13 for more details. If the 512-bit elastic buffer either

fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (256 bits) will

be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If the buffer fills, then a full frame of

data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.

11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION

The DS2153Q provides for access to both the Additional (Sa) and International (Si) bits. On the receive

side, the RAF and RNAF registers will always report the data as it received in the Additional and

International bit locations. The RAF and RNAF registers are updated with the setting of the Receive

Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the

RAF and RNAF registers. It has 250

µs to retrieve the data before it is lost.

On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit

Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the

TAF and TNAF registers. It has 250

µs to update the data or else the old data will be retransmitted. Data

in the Si bit position will be overwritten if either the DS2153Q is programmed: (1) to source the Si bits

from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa

bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1. Please see the register

descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 13 for more details.

DS2153Q Datasheet(PDF) 31 Page - Dallas Semiconductor

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