DS2153Q datasheet(16/52 Pages) DALLAS

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DS2153Q

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LOCAL LOOPBACK

When CCR2.0 is set to a 1, the DS2153Q will be forced into Local LoopBack (LLB). In this loopback,

data will continue to be transmitted as normal through the transmit side of the SCT. Data being received

at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass

through the jitter attenuator. Please see Figure 1.1 for more details.

AUTOMATIC ALARM GENERATION

When either CCR2.4 or CCR2.5 is set to 1, the DS2153Q monitors the receive side to determine if any of

the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception,

or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the

DS2151Q will either force an AIS alarm (if CCR2.5=1) or a Remote Alarm (CCR2.4=1) to be transmitted

via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1 at the same

time.

CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)

(MSB)

(LSB)

TESE

TCBFS

TIRFS

ESR

LIRST

TSCLKM

SYMBOL

POSITION

NAME AND DESCRIPTION

TESE

CCR3.7

Transmit Elastic Store Enable.

0 = elastic store is disabled

1 = elastic store is enabled

TCBFS

CCR3.6

Transmit Channel Blocking Registers (TCBR) Function

Select.

0=TCBRs define the operation of the TCHBLK output pin

1=TCBRs define which signaling bits are to be inserted

TIRFS

CCR3.5

Transmit Idle Registers (TIR) Function Select.

0=TIRs define in which channels to insert idle code

1=TIRs define in which channels to insert data from RSER

ESR

CCR3.4

Elastic Stores Reset. Setting this bit from a 1 to a 0 will force

the elastic stores to a known depth. Should be toggled after

SYSCLK has been applied and is stable. Must be set and cleared

again for a subsequent reset. Do not leave this bit set high.

LIRST

CCR3.3

Line Interface Reset. Setting this bit from a 0 to a 1 will initiate

an internal reset that affects the slicer, AGC, clock recovery state

machine, and jitter attenuator. Normally this bit is only toggled

on power-up. Must be cleared and set again for a subsequent

reset.

CCR3.2

Not Assigned. Should be set to 0 when written.

TSCLKM

CCR3.1

Transmit Backplane Clock Select. Must be set like RCR2.2.

0 = 1.544 MHz

1 = 2.048 MHz

CCR3.0

Not Assigned. Should be set to 0 when written.

DS2153Q Datasheet(PDF) 16 Page - Dallas Semiconductor

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