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CS5530A Datasheet(PDF) 187 Page - National Semiconductor (TI) |
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CS5530A Datasheet(HTML) 187 Page - National Semiconductor (TI) |
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187 / 259 page ![]() Revision 1.1 187 www.national.com Register Descriptions (Continued) Offset 20h-4Fh Reserved Reset Value = xxh Offset 50h-FFh The memory mapped registers located here (F1BAR+Memory Offset 50h-FFh) can also be accessed at F0 Index 50h-FFh. The preferred method is to program these register through the F0 register space. Refer to Table 4-15 "F0 Index xxh: PCI Header and Bridge Configuration Registers" on page 153 for bit information regarding these registers. Table 4-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued) Bit Description |
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