CS5530A datasheet(37/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Signal Definitions

Revision 1.1

DRQ[7:5],

DRQ[3:0]

Refer

Table

3-3

DMA Request - Channels 7 through 5 and 3 through 0

DRQ inputs are asserted by ISA DMA devices to request a DMA transfer.

The request must remain asserted until the corresponding DACK is

asserted.

DACK[7:5]#,

DACK[3:0]#

Refer

Table

3-3

DMA Acknowledge - Channels 7 through 5 and 3 through 0

DACK outputs are asserted to indicate when a DRQ is granted and the start

of a DMA cycle.

AF15

Terminal Count

TC signals the final data transfer of a DMA transfer.

3.2.5

ISA Bus Interface (Continued)

Signal Name

No.

Type

Description

3.2.6

ROM Interface

Signal Name

No.

Type

Description

KBROMCS#

AE4

Keyboard/ROM Chip Select

KBROMCS# is the enable pin for the BIOS ROM and for the keyboard con-

troller. For ROM accesses, KBROMCS# is asserted for ISA memory

accesses programmed at F0 Index 52h[2:0].

For keyboard controller accesses, KBROMCS# is asserted for I/O accesses

to I/O Ports 060h, 062h, 064h, and 066h.

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