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CS5530A Datasheet(PDF) 50 Page - Advanced Micro Devices

Part # CS5530A
Description  AMD Geode CS5530A Companion Device
PDF  259 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

CS5530A Datasheet(HTML) 50 Page - Advanced Micro Devices

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AMD Geode™ CS5530A Companion Device Data Book
Processor Interface
Revision 1.1
Figure 4-3. PIXEL Signal Connections
4.1.2
PSERIAL Pin Interface
The majority of the system power management logic is
implemented in the CS5530A, but a minimal amount of
logic is contained within the GX1 processor to provide
information that is not externally visible (e.g., graphics con-
troller).
The processor implements a simple serial communications
mechanism to transmit the CPU status to the CS5530A.
The processor accumulates CPU events in an 8-bit register
(defined in Table 4-1) which it transmits serially every 1 to
10 µs.
The packet transmitter holds the serial output pin (PSE-
RIAL) low until the transmission interval timer has elapsed.
Once the timer has elapsed, the PSERIAL pin is held high
for two clocks to indicate the start of packet transmission.
The contents of the Serial Packet Register are then shifted
out starting from bit 7 down to bit 0. The PSERIAL pin is
held high for one clock to indicate the end of packet trans-
mission and then remains low until the next transmission
interval. After the packet transmission is complete, the pro-
cessor’s Serial Packet Register’s contents are cleared.
The processor’s input clock is used as the clock reference
for the serial packet transmitter.
Once a bit in the register is set, it remains set until the com-
pletion of the next packet transmission. Successive events
of the same type that occur between packet transmissions
are ignored. Multiple unique events between packet trans-
missions accumulate in this register. The processor trans-
mits the contents of the serial packet only when a bit in the
Serial Packet Register is set and the interval timer has
elapsed.
For more information on the Serial Packet Register refer-
enced in Table 4-1, refer to the AMD Geode™ GX1 Proces-
sor Data Book.
The CS5530A decodes the serial packet after each trans-
mission and performs the power management tasks
related to video retrace.
4.1.2.1
Video Retrace Interrupt
Bit 7 of the “Serial Packet” can be used to generate an SMI
whenever a video retrace occurs within the processor. This
function is normally not used for power management but for
SoftVGA routines.
Setting F0 Index 83h[2] = 1 (bit details on page 164)
enables this function. A read only status register located at
F1BAR+Memory Offset 00h[5] (bit details on page 181)
can be read to see if the SMI was caused by a video
retrace event.
PIXEL17
PIXEL16
PIXEL15
PIXEL14
PIXEL13
PIXEL12
PIXEL11
PIXEL10
PIXEL9
PIXEL8
PIXEL7
PIXEL6
PIXEL5
PIXEL4
PIXEL3
PIXEL2
PIXEL1
AMD Geode™
AMD Geode™
PIXEL0
PIXEL23
PIXEL22
PIXEL21
PIXEL20
PIXEL19
PIXEL18
PIXEL17
PIXEL16
PIXEL15
PIXEL14
PIXEL13
PIXEL12
PIXEL11
PIXEL10
PIXEL9
PIXEL8
PIXEL7
PIXEL6
PIXEL5
PIXEL4
PIXEL3
PIXEL2
PIXEL1
PIXEL0
GX1
CS5530A Companion
Processor
Device
Table 4-1. GX1 Processor Serial Packet Register
Bit
Description
7
Video IRQ: This bit indicates the occurrence of a video
vertical sync pulse. This bit is set at the same time that
the VINT (Vertical Interrupt) bit gets set in the
DC_TIMING_CFG register. The VINT bit has a corre-
sponding enable bit (VIEN) in the DC_TIM_CFG regis-
ter.
6
CPU Activity: This bit indicates the occurrence of a
level 1 cache miss that was not a result of an instruc-
tion fetch. This bit has a corresponding enable bit in
the PM_CNTL_TEN register.
5:2
Reserved
1
Programmable Address Decode: This bit indicates
the occurrence of a programmable memory address
decode. The bit is set based on the values of the
PM_BASE register and the PM_MASK register. The
PM_BASE register can be initialized to any address in
the full CPU address range.
0
Video Decode: This bit indicates that the CPU has
accessed either the display controller registers or the
graphics memory region. This bit has a corresponding
enable bit in the PM_CNTRL_TEN.



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