CS5530A datasheet(68/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

When the timer decrements to zero, if power management

is enabled (F0 Index 80h[0] = 1), the timer generates an

SMI. (F0 Index 80h[0] = 0 does not disable these timers

from running, but only from generating SMI.)

When an idle timer generates an SMI, the SMI handler

manages the peripheral power, disables the timer, and

enables the trap. The next time an event occurs, the trap

generates an SMI. This time, the SMI handler applies

power to the peripheral, enables the timer (thus reloading

its starting value), and disables the trap.

Tables 4-17 through 4-25 show the device associated idle

timers and traps programming bits.

Table 4-17. Power Management Global Enabling Bits

Bit

Description

F0 Index 80h

Power Management Enable Register 1 (R/W)

Reset Value = 00h

Traps: Globally enable all power management device I/O traps. 0 = Disable; 1 = Enable.

This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h.

Idle Timers: Globally enable all power management device idle timers. 0 = Disable; 1 = Enable.

Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.

This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h), nor on the General Purpose (UDEFx)

Timers (F0 Index 88h-8Bh). This bit must be set for the command to trigger the SUSP#/SUSPA# feature to function (see F0

Index AEh).

Power Management: Global power management. 0 = Disable; 1 = Enabled.

This bit must be set (1) immediately after POST for some power management resources to function. Until this is done, the

command to trigger the SUSP#/SUSPA# feature is disabled (see F0 Index AEh) and all SMI# trigger events listed for

F0 Index 84h-87h are disabled. A ‘0’ in this bit does NOT stop the Idle Timers if bit 1 of this register is a ‘1’, but only prevents

them from generating an SMI# interrupt. It also has no effect on the UDEF traps.

Table 4-18. Keyboard/Mouse Idle Timer and Trap Related Registers

Bit

Description

F0 Index 81h

Power Management Enable Register 2 (R/W)

Reset Value = 00h

Keyboard/Mouse Idle Timer Enable: Load timer from Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and gen-

erate an SMI when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count.

Keyboard Controller: I/O Ports 060h/064h

COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included)

COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[3].

F0 Index 82h

Power Management Enable Register 3 (R/W)

Reset Value = 00h

Keyboard/Mouse Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated.

Keyboard Controller: I/O Ports 060h/064h

COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included)

COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[3].

F0 Index 93h

Miscellaneous Device Control Register (R/W)

Reset Value = 00h

Mouse on Serial Enable: Mouse is present on a serial port. 0 = No; 1 = Yes. (Note)

Mouse Port Select: Selects which serial port the mouse is attached to. 0 = COM1; 1 = COM2. (Note)

Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to

monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a

mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen.

These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Parallel/

Serial Port Idle Timer Count Register (F0 Index 9Ch).

CS5530A Datasheet(PDF) 68 Page - Advanced Micro Devices

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