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CS5530A Datasheet(PDF) 40 Page - Advanced Micro Devices |
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CS5530A Datasheet(HTML) 40 Page - Advanced Micro Devices |
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40 / 259 page ![]() 40 AMD Geode™ CS5530A Companion Device Data Book Signal Definitions Revision 1.1 GPIO1/ SDATA_IN2 AE24 I/O General Purpose I/O 1 or Serial Data Input 2 This pin can function either as a general purpose I/O or as a second serial data input pin if two codecs are used in the system. In order for this pin to function as SDATA_IN2, it must first be configured as an input (F0 Index 90h[1] = 0). Then setting F3BAR+Memory Offset 08h[21] = 1 selects the pin to function as SDATA_IN2. Refer to GPIO[3:2] signal description for GPIO function description. GPIO0 AC22 I/O General Purpose I/O 0 Refer to GPIO[3:2] signal description for GPIO function description. 3.2.9 Game Port and General Purpose I/O Interface (Continued) Signal Name Pin No. Pin Type Description 3.2.10 Audio Interface Signal Name Pin No. Pin Type Description BIT_CLK V2 I Audio Bit Clock The serial bit clock from the codec. SDATA_OUT V1 O Serial Data I/O This output transmits audio serial data to the codec. SDATA_IN U4 I Serial Data Input This input receives serial data from the codec. SYNC U3 O Serial Bus Synchronization This bit is asserted to synchronize the transfer of data between the CS5530A and the AC97 codec. PC_BEEP V3 O PC Beep Legacy PC/AT speaker output. 3.2.11 Display Interface Signal Name Pin No. Pin Type Description Pixel Port PCLK A13 I Pixel Clock This clock is used to sample data on the PIXEL input port. It runs at the graphics DOT clock (DCLK) rate. PIXEL[23:0] Refer to Table 3-3 I Pixel Data Port This is the input pixel data from the processor’s display controller. If F4BAR+Memory Offset 00h[29] is reset, the data is sent in RGB 8:8:8 for- mat. Otherwise, the pixel data is sent in RGB 5:6:5 format which has been dithered by the processor. The other eight bits are used in conjunction with VID_DATA[7:0] to provide 16-bit video data. This bus is sampled by the PCLK input. |
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