CS5530A datasheet(41/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Signal Definitions

Revision 1.1

ENA_DISP

Display Enable Input

This signal qualifies active data on the pixel input port. It is used to qualify

active pixel data for all display modes and configurations and is not specific

to flat panel display.

Display CRT

HSYNC

Horizontal Sync Input

This is the CRT horizontal sync input from the processor’s display controller.

It is used to indicate the start of a new video line. This signal is pipelined for

the appropriate number of clock stages to remain in sync with the pixel data.

A separate output (HSYNC_OUT) is provided to re-drive the CRT and flat

panel interfaces.

HSYNC_OUT

Horizontal Sync Output

This is the horizontal sync output to the CRT. It represents a delayed version

of the input horizontal sync signal with the appropriate pipeline delay relative

to the pixel data. The pipeline delay and polarity of this signal are program-

mable.

VSYNC

Vertical Sync Input

This is the CRT vertical sync input from the processor’s display controller. It

is used to indicate the start of a new frame. This signal is pipelined for the

appropriate number of clock stages to remain in sync with the pixel data. A

separate output (VSYNC_OUT) is provided to re-drive the CRT and flat

panel interfaces.

VSYNC_OUT

Vertical Sync Output

This is the vertical sync output to the CRT. It represents a delayed version of

the input vertical sync signal with the appropriate pipeline delay relative to

the pixel data. The pipeline delay and polarity of this signal are programma-

ble.

DDC_SCL

DDC Serial Clock

This is the serial clock for the VESA Display Data Channel interface. It is

used for monitoring communications. The DDC2B standard is supported by

this interface.

DDC_SDA

I/O

DDC Serial Data

This is the bidirectional serial data signal for the VESA Display Data Chan-

nel interface. It is used to monitor communications. The DDC2B standard is

supported by this interface.

The direction of this pin can be configured through F4BAR+Memory Offset

04h[24]: 0 = Input; 1 = Output.

IREF

(Video DAC)

Analog

VDAC Current Reference Input

Connect a 680 ohm resistor between this pin and AVSS (analog ground for

Video DAC).

EXTVREFIN

(Video DAC)

Analog

External Voltage Reference Pin

Connect this pin to a 1.235V voltage reference.

3.2.11

Display Interface (Continued)

Signal Name

No.

Type

Description

CS5530A Datasheet(PDF) 41 Page - Advanced Micro Devices

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