CS5530A datasheet(63/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

4.4.1.6

Suspend Modulation

Suspend Modulation is a derivative of the On and Suspend

states and works by asserting and de-asserting the SUSP#

pin to the CPU for a configurable period and duty cycle. By

modulating the SUSP# pin, an effective reduction in fre-

quency is achieved. Suspend Modulation is the system

power management choice of last resort. However, it is an

excellent choice for thermal management. If the system is

expected to operate in a thermal environment where the

processor could overheat, then Suspend Modulation could

be used to reduce power consumption in the overheated

condition and thus reduce the processor’s temperature.

When used as a power management state, Suspend Mod-

ulation works by assuming that the processor is idle unless

external activity indicates otherwise. This approach effec-

tively slows down the processor until external activity indi-

cates a need to run at full speed, thereby reducing power

consumption.

Suspend Modulation serves as the primary CPU power

management mechanism when APM or some other power

management software strategy is not present. It can also

act as a backup for situations where the power manage-

ment scheme does not correctly detect an Idle condition in

the system.

In order to provide high-speed performance when needed,

the SUSP# pin modulation can be temporarily disabled any

time system activity is detected. When this happens, the

processor is “instantly” converted to full speed for a pro-

grammed duration. System activities in the CS5530A are

defined in hardware as: any unmasked IRQ, accessing

Port 061h, SMI, and/or accessing the graphics controller.

Since the graphics controller is integrated in the GX1 pro-

cessor, the indication of graphics activity is sent to the

CS5530A via the serial link (see Section 4.1.2 "PSERIAL

Pin Interface" on page 50 for more information on serial

link) and is automatically decoded. Graphics activity is

defined as any access to the VGA register space, the VGA

frame buffer, the graphics accelerator control registers and

the configured graphics frame buffer.

The automatic speedup events (IRQ, SMI, and/or graphics)

for Suspend Modulation should be used together with soft-

ware-controlled speedup registers for major I/O events

such as any access to the floppy disk controller, hard disk

drive, or parallel/serial ports, since these are indications of

major system activities. When major I/O events occur, Sus-

pend Modulation can be temporarily disabled using the

procedures described in the following subsections.

Bus master internal (Ultra DMA/33, Audio, USB, or ISA) or

external requests do not directly affect the Suspend Modu-

lation programming.

Configuring Suspend Modulation

Control of the Suspend Modulation feature is accomplished

using the Suspend Modulation OFF Count Register, the

Suspend Modulation ON Count Register, and the Suspend

Configuration Register (F0 Index 94h, 95h, and 96h,

respectively).

The Power Management Enable Register 1 (F0 Index 80h)

contains the enables for the individual activity speedup tim-

ers.

Bit 0 of the Suspend Configuration Register (F0 Index 96h)

enables the Suspend Modulation feature. Bit 1 controls

how SMI events affect the Suspend Modulation feature. In

general this bit should be set to a 1, which causes SMIs to

disable Suspend Modulation until it is re-enabled by the

SMI handler.

The Suspend Modulation OFF and ON Count Registers

(F0 Index 94h and 95h) control two 8-bit counters that rep-

resent the number of 32 µs intervals that the SUSP# pin is

asserted and then deasserted to the processor. These

counters define a ratio which is the effective frequency of

operation of the system while Suspend Modulation is

enabled.

The IRQ and Video Speedup Timer Count registers (F0

Index 8Ch and 8Dh) configure the amount of time which

Suspend Modulation is disabled when the respective

events occur.

SMI Speedup Disable

If the Suspend Modulation feature is being used for CPU

power management, the occurrence of an SMI disables the

Suspend Modulation function so that the system operates

at full speed while in SMM. There are two methods used to

invoke this via bit 1 of the Suspend Configuration Register.

If F0 Index 96h[1] = 0: Use the IRQ Speedup Timer (F0

Index 8Ch) to temporarily disable Suspend Modulation

when an SMI occurs.

If F0 Index 96h[1] = 1: Disable Suspend Modulation when

an SMI occurs until a read to the SMI Speedup Disable

The SMI Speedup Disable Register prevents VSA technol-

ogy software from entering Suspend Modulation while

operating in SMM. The data read from this register can be

ignored. If the Suspend Modulation feature is disabled,

reading this I/O location has no effect.

Table 4-14 shows the bit formats of the Suspend Modula-

tion related registers.

Feff = FGX86 x

Off Count

On Count + Off Count

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