CS5530A datasheet(67/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

4.4.2

APM Support

Some IA systems rely solely on an APM (Advanced Power

Management) driver for enabling the operating system to

power-manage the CPU. APM provides several services

which enhance the system power management and is the-

oretically the best approach; but in its current form, APM is

imperfect for the following reasons:

• APM is an OS-specific driver, and may not be available

for some operating systems.

• Application support is inconsistent. Some applications in

foreground may prevent Idle calls.

• APM does not help with Suspend determination or

peripheral power management.

The CS5530A provides two entry points for APM support:

• Software CPU Suspend control via the CPU Suspend

Command Register (F0 Index AEh)

• Software SMI entry via the Software SMI Register (F0

Index D0h). This allows the APM BIOS to be part of the

SMI handler.

These registers are shown in Table 4-16.

4.4.3

Peripheral Power Management

The CS5530A provides peripheral power management

using a combination of device idle timers, address traps,

and general purpose I/O pins. Idle timers are used in con-

junction with traps to support powering down peripheral

devices. Eight programmable GPIO (general purpose I/O)

pins are included for external device power control as well

as other functions. All I/O addresses are decoded in 16

bits. All memory addresses are decoded in 32 bits.

4.4.3.1

Device Idle Timers and Traps

Idle timers are used to power manage a peripheral by

determining when the peripheral has been inactive for a

specified period of time, and removing power from the

peripheral at the end of that time period.

Idle timers are provided for the commonly-used peripherals

(FDC, IDE, parallel/serial ports, and mouse/keyboard). In

addition, there are three user-defined timers that can be

configured for either I/O or memory ranges. The Power

Management enable bit (F0 Index 80h[1]) enables and dis-

ables the power management idle timers. The Trap bit in

the same register (F0 Index 80h[2]) enables and disables

device I/O traps.

The idle timers are 16-bit countdown timers with a 1 sec-

ond time base, providing a time-out range of 1 to 65536

seconds (1092 minutes) (18 hours). General purpose tim-

ers can be programmed to count milliseconds instead of

seconds (see Section 4.4.3.2 on page 77 for further infor-

mation on general purpose timers).

When the idle timers are enabled, the timers are loaded

from the timer count registers and start to decrement at the

next timebase clock, but cannot trigger an interrupt on that

cycle. If an idle timer is initially set to 1, it decrements to 0

on the first cycle and continues counting with 65535 on the

next cycle. Starting at 2 gives 1 on the first cycle, and 0 on

the second cycle, generating the interrupt. Since the time-

base is one second, the minimum interval before the next

interrupt from this timer is variable, from one to two sec-

onds with a setting of two.

The idle timers continue to decrement until one of two pos-

sibilities occurs: a bus cycle occurs at that I/O or memory

range, or the timer decrements to zero.

When a bus cycle occurs, the idle timer is reloaded with its

starting value. It then continues to decrement.

Table 4-16. APM Support Registers

Bit

Description

F0 Index AEh

CPU Suspend Command Register (WO)

Reset Value = 00h

7:0

Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] =

0) and all SMI status bits are 0, a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU

in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt con-

dition.

If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after

the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is invoked,

allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the

only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI

source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake-

up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI

events are also Resume events.

F0 Index D0h

Software SMI Register (WO)

Reset Value = 00h

7:0

Software SMI (Write Only): A write to this location generates an SMI. The data written is irrelevant. This register allows

software entry into SMM via normal bus access instructions.

CS5530A Datasheet(PDF) 67 Page - Advanced Micro Devices

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