CS5530A datasheet(92/259 Pages) AMD

92 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

PC/AT Compatibility Logic

Revision 1.1

4.5.2.2

Limited ISA and ISA Master Modes

The CS5530A supports two modes on the ISA interface.

The default mode of the ISA bus is a fully functional ISA

mode, but it does not support ISA masters, as shown in

Figure 4-10 "Limited ISA Mode". When in this mode, the

address and data buses are multiplexed together, requiring

an external latch to latch the lower 16 bits of address of the

ISA cycle. The signal SA_LATCH is generated when the

data on the SA/SD bus is a valid address. Additionally, the

upper four address bits, SA[23:20], are multiplexed on

GPIO[7:4].

The second mode of the ISA interface supports ISA bus

masters, as shown in Figure 4-11. When the CS5530A is

placed in the ISA Master mode, a large number of pins are

redefined as shown in Table 4-37.

In this mode of operation, the CS5530A cannot support

TFT flat panels or TV controllers, since most of the signals

used to support these functions have been redefined. This

mode is required if ISA slots or ISA masters are used. ISA

master cycles are only passed to the PCI bus if they

access memory. I/O accesses are left to complete on the

ISA bus.

The mode of operation is selected by the strapping of pin

P26 (INTR):

• ISA Limited Mode — Strap pin P26 (INTR) low through a

10-kohm resistor.

• ISA Master Mode — Strap pin P26 (INTR) high through

a 10-kohm resistor.

F0 Index 44h[7] (bit details on page 158) reports the strap

value of the INTR pin (pin P26) during POR: 0 = ISA Lim-

ited; 1 = ISA Master.

This bit can be written after POR# deassertion to change

the ISA mode selected. Writing to this bit is not recom-

mended due to the actual strapping done on the board.

ISA memory and ISA refresh cycles are not supported by

the CS5530A,

although, the refresh toggle bit in I/O Port

061h still exists for software compatibility reasons.

Note:

If Limited ISA Mode of operation has been

selected, SMEMW# and SMEMR# can be output

on these pins by programming F0 Index 53[2] = 0

(bit details on page 159).

Table 4-37. Signal Assignments

Pin No.

Limited ISA Mode

ISA Master

Mode

AD15

SA_LATCH

SA_DIR

AE25, AD24,

AE22, AE21,

AF21, AC20,

AD19, AF19,

AF4, AF5,

AD5, AF6,

AC6, AD9,

AE6, AE9

SA[15:0]/SD[15:0]

SD[15:0]

H2, K1, K2,

L1, D1, E2,

F1, G1, G3,

G4, G2, H1,

J1, J3, J2, K3

FP_DATA[15:0]

SA[15:0]

FP_DATA[16]

SA_OE#

FP_DATA[17]

MASTER#

FP_HSYNC_OUT

SMEMW#

FP_VSYNC_OUT

SMEMR#

AF3 (Note)

SMEMW#

RTCCS#

AD4 (Note)

SMEMR#

RTCALE

AF23, AE23,

AC21, AD22

GPIO[7:4]

SA[23:20]

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