CS5530A datasheet(94/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

PC/AT Compatibility Logic

Revision 1.1

4.5.2.3

ISA Bus Data Steering

The CS5530A performs all of the required data steering

from SD[7:0] to SD[15:0] during normal 8-bit ISA cycles, as

well as during DMA and ISA master cycles. It handles data

transfers between the 32-bit PCI data bus and the ISA bus.

8/16-bit devices can reside on the ISA bus. Various PC-

compatible I/O registers, DMA controller registers, interrupt

controller registers, and count registers (for loading timers)

lie on the on-chip I/O data bus. Either the PCI bus master

or the DMA controllers can become the bus owner.

When the PCI bus master is the bus owner, the CS5530A

data steering logic provides data conversion necessary for

8/16/32-bit transfers to and from 8/16-bit devices on either

the ISA bus or the 8-bit registers on the on-chip I/O data

bus. When PCI data bus drivers of the CS5530A are

tristated, data transfers between the PCI bus master and

PCI bus devices are handled directly via the PCI data bus.

When the DMA requestor is the bus owner, the CS5530A

allows 8/16-bit data transfer between the ISA bus and the

PCI data bus.

4.5.2.4

I/O Recovery Delays

In normal operation, the CS5530A inserts a delay between

back-to-back ISA I/O cycles that originate on the PCI bus.

The default delay is four ISACLK cycles. Thus, the second

of consecutive I/O cycles is held in the ISA bus controller

until this delay count has expired. The delay is measured

between the rising edge of IOR#/IOW# and the falling edge

of BALE. This delay can be adjusted to a greater delay

through the ISA I/O Recovery Control Register (F0 Index

51h, see Table 4-38).

Note:

This delay is not inserted for a 16-bit ISA I/O

access that is split into two 8-bit I/O accesses.

Table 4-38. I/O Recovery Programming Register

Bit

Description

F0 Index 51h

ISA I/O Recovery Control Register (R/W)

Reset Value = 40h

7:4

8-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This

count is in addition to a preset one-clock delay built into the controller.

0000 = 1 ISA clock

0100 = 5 ISA clocks

1000 = 9 ISA clocks

1100 = 13 ISA clocks

0001 = 2 ISA clocks

0101 = 6 ISA clocks

1001 = 10 ISA clocks

1101 = 14 ISA clocks

0010 = 3 ISA clocks

0110 = 7 ISA clocks

1010 = 11 ISA clocks

1110 = 15 ISA clocks

0011 = 4 ISA clocks

0111 = 8 ISA clocks

1011 = 12 ISA clocks

1111 = 16 ISA clocks

3:0

16-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This