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CS5530A Datasheet(PDF) 44 Page - Advanced Micro Devices |
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CS5530A Datasheet(HTML) 44 Page - Advanced Micro Devices |
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44 / 259 page ![]() 44 AMD Geode™ CS5530A Companion Device Data Book Signal Definitions Revision 1.1 FP_DISP_ ENA_OUT F2 O Flat Panel Display Enable Output This is the display enable for an attached active matrix TFT flat panel. This signal qualifies active pixel data on the flat panel interface. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. FP_ENA_VDD L2 O Flat Panel VDD Enable This is the enable signal for the VDD supply to an attached flat panel. It is under the control of power sequence control logic. A transition on bit 6 of the Display Configuration Register (F4BAR+Memory Offset 04h) initiates a power-up/down sequence. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. FP_ENA_BKL J4 O Flat Panel Backlight Enable Output This is the enable signal for the backlight power supply to an attached flat panel. It is under control of the power sequence control logic. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. Display MPEG VID_DATA[7:0] C12, B12, A12, D11, C11, B13, C13, A11 I Video Data Port This is the input data for a video (MPEG) or graphics overlay in its native form. For video overlay, this data is in an interleaved YUV 4:2:2 format. For graphics overlay, the data is in RGB 5:6:5 format. This port operates at the VID_CLK rate. VID_CLK A6 I Video Clock This is the clock for the video port. This clock is completely asynchronous to the input pixel clock rate. VID_VAL B7 I Video Valid This signal indicates that valid video data is being presented on the VID_DATA input port. If the VID_RDY signal is also asserted, the data will advance. VID_RDY B10 O Video Ready This signal indicates that the CS5530A is ready to receive the next piece of video data on the VID_DATA port. If the VID_VAL signal is also asserted, the data will advance. 3.2.11 Display Interface (Continued) Signal Name Pin No. Pin Type Description |
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