CS5530A datasheet(42/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Signal Definitions

Revision 1.1

AVDD1 (DAC)

Analog

Analog Power for Video DAC

These pins provide power to the analog portions of the Video DAC.

A 47 µF capacitor should be connected between the DAC analog power and

DAC analog ground. Analog power is AVDD1 (pin U1) and AVDD3 (pin N4).

Analog ground is AVSS1 (pin R2) and AVSS5 (pin P2).

AVDD2 (VREF)

AVDD3 (DAC)

AVSS1 (DAC)

Analog

Analog Ground for Video DAC

These pins provide the ground plane connections to the analog portions of

the Video DAC.

A 47 µF capacitor should be connected between the DAC analog power and

DAC analog ground. Analog power is AVDD1 (pin U1) and AVDD3 (pin N4).

Analog ground is AVSS1 (pin R2) and AVSS5 (pin P2).

AVSS2 (ICAP)

AVSS3 (VREF)

AVSS4 (ICAP)

AVSS5 (DAC)

IOUTR

(Video DAC)

Analog

Red DAC Output

Red analog output.

IOUTG

(Video DAC)

Analog

Green DAC Output

Green analog output.

IOUTB

(Video DAC)

Analog

Blue DAC Output

Blue analog output.

Display TFT/TV

FP_DATA17/

MASTER#

Limited ISA Mode: Flat Panel Data Port Line 17

Refer to FP_DATA[15:0] signal description.

ISA Master Mode: Master

Refer to Section 3.2.5 "ISA Bus Interface" on page 34 for this signal’s defini-

tion.

FP_DATA16/

SA_OE#

Limited ISA Mode: Flat Panel Data Port Line 16

Refer to FP_DATA[15:0] signal description.

ISA Master Mode: System Address Transceiver Output Enable

Refer to Section 3.2.5 "ISA Bus Interface" on page 34 for this signal’s defini-

tion.

FP_DATA[15:0]/

SA[15:0]

Refer

Table

3-3

Limited ISA Mode: Flat Panel Data Port Lines 15 through 0

This is the data port to an attached active matrix TFT panel. This port may

optionally be tied to a DSTN formatter chip, LVDS transmitter, or digital

NTSC/PAL encoder.

F4BAR+Memory Offset 04h[7] enables the flat panel data bus:

0 = FP_DATA[17:0] is forced low

1 = FP_DATA[17:0] is driven based upon power sequence control

I/O

ISA Master Mode: System Address Bus Lines 15 through 0

These pins function as SA[15:0] and the pins designated as SA/SD[15:0]

function only as SD[15:0].

Note that SA[19:16] are dedicated address pins and GPIO[7:4] function as

SA[23:20] only.

3.2.11

Display Interface (Continued)

Signal Name

No.

Type

Description

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