CS5530A datasheet(95/259 Pages) AMD

95 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

PC/AT Compatibility Logic

Revision 1.1

4.5.2.5

ISA DMA

DMA transfers occur between ISA I/O peripherals and sys-

tem memory. The data width can be either 8 or 16 bits. Out

of the seven DMA channels available, four are used for 8-

bit transfers while the remaining three are used for 16-bit

transfers. One BYTE or WORD is transferred in each DMA

cycle.

Note:

The CS5530A does not support DMA transfers to

ISA memory.

The ISA DMA device initiates a DMA request by asserting

one of the DRQ[7:5, 3:0] signals. When the CS5530A

receives this request, it sends a bus grant request to the

PCI arbiter. After the PCI bus has been granted, the

respective DACK# is driven active.

The CS5530A generates PCI memory read or write cycles

in response to a DMA cycle. Figures 4-12 and 4-13 are

examples of DMA memory read and memory write cycles.

Upon detection of the DMA controller’s MEMR# or MEMW#

active, the CS5530A starts the PCI cycle, asserts

FRAME#, and negates an internal IOCHRDY. This assures

the DMA cycle does not complete before the PCI cycle has

provided or accepted the data. IOCHRDY is internally

asserted when IRDY# and TRDY# are sampled active.

Figure 4-12. ISA DMA Read from PCI Memory

Figure 4-13. ISA DMA Write To PCI Memory

PCICLK

ISACLK

MEMR#

IOW#

FRAME#

AD[31:0]

IRDY#

TRDY#

SD[15:0]

IOCHRDY

PCICLK

ISACLK

MEMW#

IOR#

FRAME#

AD[31:0]

IRDY#

TRDY#

SD[15:0]

IOCHRDY

CS5530A Datasheet(PDF) 95 Page - Advanced Micro Devices

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